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参数资料
| 型号： | 24AA02T-I/SM |
| 元件分类： | PROM |
| 英文描述： | 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封装： | 0.207 INCH, PLASTIC, SOIC-8 |
| 文件页数： | 8/13页 |
| 文件大小： | 191K |
| 代理商： | 24AA02T-I/SM |
24AA01/02
DS21052H-page 4
1998 Microchip Technology Inc.
2.0
FUNCTIONAL DESCRIPTION
The 24AA01/02 supports a bi directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is dened as transmitter, and a
device receiving data as receiver. The bus has to be
controlled by a master device which generates the
serial clock (SCL), controls the bus access, and gener-
ates the START and STOP conditions, while the
24AA01/02 works as slave. Both, master and slave can
operate as transmitter or receiver but the master device
determines which mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been dened:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
dened (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a rst in rst
out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
Note:
The 24AA01/02 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
(A)
(B)
(D)
(A)
(C)
DSCL
or
MSCL
DSCL
or
MSCL
START
CONDITION
ADDRESS OR
ACKNOWLEDGE
VALID
DATA
ALLOWED
TO CHANGE
STOP
CONDITION
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相关代理商/技术参数 |
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|---|---|
| 24AA02UID | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:2K I2Ca?￠ Serial EEPROMs with Unique 32-bit Serial Number |
| 24AA02UID-I/P | 功能描述:电可擦除可编程只读存储器 2K I2C EE Unique ID RoHS:否 制造商:Intersil 存储容量: 组织: 数据保留: 最大时钟频率: 最大工作电流: 工作电源电压: 最大工作温度: 安装风格: 封装 / 箱体: |
| 24AA02UID-I/SN | 功能描述:电可擦除可编程只读存储器 2K I2C EE Unique ID RoHS:否 制造商:Intersil 存储容量: 组织: 数据保留: 最大时钟频率: 最大工作电流: 工作电源电压: 最大工作温度: 安装风格: 封装 / 箱体: |
| 24AA02UIDT-I/OT | 功能描述:电可擦除可编程只读存储器 2K I2C EE Unique ID RoHS:否 制造商:Intersil 存储容量: 组织: 数据保留: 最大时钟频率: 最大工作电流: 工作电源电压: 最大工作温度: 安装风格: 封装 / 箱体: |
| 24AA02UIDT-I/SN | 功能描述:电可擦除可编程只读存储器 2K I2C EE Unique ID RoHS:否 制造商:Intersil 存储容量: 组织: 数据保留: 最大时钟频率: 最大工作电流: 工作电源电压: 最大工作温度: 安装风格: 封装 / 箱体: |
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