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参数资料
| 型号： | 24AA02T-I/SM |
| 元件分类： | PROM |
| 英文描述： | 256 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8 |
| 封装： | 0.207 INCH, PLASTIC, SOIC-8 |
| 文件页数： | 9/13页 |
| 文件大小： | 191K |
| 代理商： | 24AA02T-I/SM |
24AA01/02
1998 Microchip Technology Inc.
DS21052H-page 5
3.6
Device Address
The 24AA01/02 are software-compatible with older
devices such as 24C01A, 24C02A, 24LC01, and
24LC02. A single 24AA02 can be used in place of two
24LC01's, for example, without any modications to
software. The “chip select” portion of the control byte
becomes a don't care.
After generating a START condition, the bus master
transmits the slave address consisting of a 4-bit device
code (1010) for the 24AA01/02, followed by three don't
care bits.
The eighth bit of slave address determines if the master
device wants to read or write to the 24AA01/02
The 24AA01/02 monitors the bus for its corresponding
slave address all the time. It generates an acknowledge
bit if the slave address was true and it is not in a pro-
gramming mode.
FIGURE 3-2:
CONTROL BYTE
ALLOCATION
4.0
WRITE OPERATION
4.1
Byte Write
Following the start signal from the master, the device
code (4 bits), the don't care bits (3 bits), and the R/W
bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed
slave receiver that a byte with a word address will follow
after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the word address and will be written into
the address pointer of the 24AA01/02. After receiving
another acknowledge signal from the 24AA01/02 the
master device will transmit the data word to be written
into the addressed memory location. The 24AA01/02
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24AA01/02 will not generate acknowl-
edge signals (Figure 4-1).
4.2
Page Write
The write control byte, word address and the rst data
byte are transmitted to the 24AA01/02 in the same way
as in a byte write. But instead of generating a stop con-
dition the master transmits up to eight data bytes to the
24AA01/02 which are temporarily stored in the on-chip
page buffer and will be written into the memory after the
master has transmitted a stop condition. After the
receipt of each word, the three lower order address
pointer bits are internally incremented by one. The
higher order ve bits of the word address remains con-
stant. If the master should transmit more than eight
words prior to generating the stop condition, the
address counter will roll over and the previously
received data will be overwritten. As with the byte write
operation, once the stop condition is received an inter-
nal write cycle will begin (Figure 7-1).
Operation
Control
Code
Chip Select
R/W
Read
1010
XXX
1
Write
1010
XXX
0
SLAVE ADDRESS
X = Don’t care
101
0X
X
R/W
A
START
READ/WRITE
Note:
Page write operations are limited to writing
bytes within a single physical page, regard-
less of the number of bytes actually being
written. Physical page boundaries start at
addresses that are integer multiples of the
page buffer size (or page size) and end at
addresses that are integer multiples of
[page size - 1]. If a page write command
attempts to write across a physical page
boundary, the result is that the data wraps
around to the beginning of the current page
(overwriting data previously stored there),
instead of being written to the next page as
might be expected. It is therefore neces-
sary for the application software to prevent
page write operations that would attempt to
cross a page boundary.
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