参数资料
| 型号： | 24AA08H-I/P |
| 厂商： | Microchip Technology |
| 文件页数： | 5/28页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 8KBIT 400KHZ 8DIP |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 60 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 8K (4 x 256 x 8) |
| 速度： | 100kHz，400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-DIP（0.300"，7.62mm） |
| 供应商设备封装： | 8-PDIP |
| 包装： | 管件 |
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24AA08H/24LC08BH
2.0
FUNCTIONAL DESCRIPTION
3.4
Data Valid (D)
The 24XX08H supports a bidirectional, 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, while a device
receiving data is defined as a receiver. The bus has to
be controlled by a master device which generates the
Serial Clock (SCL), controls the bus access and
generates the Start and Stop conditions, while the
24XX08H works as slave. Both master and slave can
operate as transmitter or receiver, but the master
device determines which mode is activated.
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is
3.0
BUS CHARACTERISTICS
theoretically unlimited, although only the last sixteen
will be stored when doing a write operation. When an
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
is not busy.
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
overwrite does occur it will replace data in a first-in first-
out (FIFO) fashion.
3.5 Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this Acknowledge bit.
defined (Figure 3-1).
Note:
The 24XX08H does not generate any
Acknowledge bits if an internal program-
3.1
Bus Not Busy (A)
ming cycle is in progress.
Both data and clock lines remain high.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
3.2
Start Data Transfer (B)
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
course, setup and hold times must be taken into
account. During reads, a master must signal an end of
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
3.3
Stop Data Transfer (C)
In this case, the slave (24XX08H) will leave the data
line high to enable the master to generate the Stop
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
condition.
FIGURE 3-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
SCL
(A)
(B)
(D)
(D)
(C)
(A)
SDA
Start
Condition
? 2008 Microchip Technology Inc.
Address or
Acknowledge
Valid
Data
Allowed
to Change
Stop
Condition
DS22084A-page 5
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