参数资料
型号: 24AA52-I/P
厂商: Microchip Technology
文件页数: 12/36页
文件大小: 0K
描述: IC EEPROM 2KBIT 400KHZ 8DIP
产品培训模块: I2C Serial EEPROM
标准包装: 60
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 2K (256 x 8)
速度: 100kHz,400kHz
接口: I²C,2 线串口
电源电压: 1.8 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
其它名称: 24AA52I/P
24AA52/24LCS52
8.0
READ OPERATION
8.3
Sequential Read
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to ‘ 1 ’. There are three basic types
of read operations: current address read, random read
and sequential read.
Sequential reads are initiated in the same way as a
random read, with the exception that after the 24XXX52
transmits the first data byte, the master issues an
acknowledge, as opposed to a Stop condition in a
random read. This directs the 24XXX52 to transmit the
8.1
Current Address Read
next sequentially addressed 8-bit word (Figure 8-3).
To provide sequential reads, the 24XXX52 contains an
The 24XXX52 contains an address counter that
maintains the address of the last word accessed, inter-
nally incremented by ‘ 1 ’. Therefore, if the previous
access (either a read or write operation) was to
address n , the next current address read operation
would access data from address n+1 . Upon receipt of
the slave address with R/W bit set to ‘ 1 ’, the 24XXX52
issues an acknowledge and transmits the 8-bit data
word. The master will not acknowledge the transfer, but
does generate a Stop condition and the 24XXX52
discontinues transmission (Figure 8-1).
internal Address Pointer, which is incremented by one
at the completion of each operation. This Address
Pointer allows the entire memory contents to be serially
read during one operation.
8.4 Contiguous Addressing Across
Multiple Devices
The Chip Select bits (A2, A1, A0) can be used to
expand the contiguous address space for up to 16K bits
by adding up to eight 24XXX52 devices on the same
bus. In this case, software can use A0 of the control
8.2
Random Read
byte as address bit A8; A1 as address bit A9, and A2
as address bit A10. It is not possible to sequentially
Random read operations allow the master to access
read across device boundaries.
any memory location in a random manner. To perform
this type of read operation, the word address must first
8.5
Noise Protection and Brown-Out
be set. This is done by sending the word address to the
24XXX52 as part of a write operation. Once the word
address is sent, the master generates a Start condition
following the acknowledge. This terminates the write
operation, but not before the internal Address Pointer is
set. The master then issues the control byte again, but
with the R/W bit set to a ‘ 1 ’. The 24XXX52 then issues
an acknowledge and transmits the 8-bit data word. The
master will not acknowledge the transfer, but does
generate a Stop condition and the 24XXX52
discontinues transmission (Figure 8-2).
The 24XXX52 employs a V CC threshold detector circuit
which disables the internal erase/write logic if the V CC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
FIGURE 8-1:
CURRENT ADDRESS READ
Bus Activity
Master
S
T
A
R
T
Control
Byte
Data (n)
S
T
O
P
SDA Line
Bus Activity
DS21166K-page 12
S
A
C
K
P
N
O
A
C
K
? 1996-2011 Microchip Technology Inc.
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