参数资料
型号: 24C65/P
厂商: Microchip Technology
文件页数: 4/24页
文件大小: 0K
描述: IC EEPROM 64KBIT 400KHZ 8DIP
产品培训模块: I2C Serial EEPROM
标准包装: 60
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 64K (8K x 8)
速度: 400kHz
接口: I²C,2 线串口
电源电压: 4.5 V ~ 6 V
工作温度: 0°C ~ 70°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
产品目录页面: 1447 (CN2011-ZH PDF)
24AA65/24LC65/24C65
TABLE 1-2:
AC CHARACTERISTICS
V CC = 1.8V-6.0V
V CC = 4.5-6.0V
Parameter
Symbol
STD. Mode
Min
Max
FAST Mode
Min
Max
Units
Remarks
Clock frequency
Clock high time
Clock low time
F CLK
T HIGH
T LOW
4000
4700
100
600
1300
400
kHz
ns
ns
SDA and SCL rise time
SDA and SCL fall time
Start condition setup time
T R
T F
T HD : STA
4000
1000
300
600
300
300
ns
ns
ns
(Note 1)
(Note 1)
After this period the first
clock pulse is generated
Start condition setup time
T SU : STA
4700
600
ns
Only relevant for
repeated Start condition
Data input hold time
Data input setup time
Stop condition setup time
T HD : DAT
T SU : DAT
T SU : STO
0
250
4000
0
100
600
ns
ns
ns
Output valid from clock
Bus free time
T AA
T BUF
4700
3500
1300
900
ns
ns
(Note 2)
Time the bus must be
free before a new
transmission can start
Output fall time from V IH min to T OF
V IL max
— 250 20 + 0.1
C B
250 ns
(Note 1) , C B ≤ 100 pF
Input filter spike suppression
T SP
50 — 50 — ns
(Note 3)
(SDA and SCL pins)
Write cycle time T WR
Endurance
— 5 — 5 ms/page (Note 4)
High Endurance Block
Rest of Array
10M
1M
10M
1M
cycles 25°C, (Note 5)
Note 1:
2:
3:
4:
5:
Not 100 percent tested. C B = total capacitance of one bus line in pF.
As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
The combined T SP and V HYS specifications are due to new Schmitt Trigger inputs which provide improved
noise and spike suppression. This eliminates the need for a Ti specification for standard operation.
The times shown are for a single page of 8 bytes. Multiply by the number of pages loaded into the write
cache for total time.
This parameter is not tested but ensured by characterization. For endurance estimates in a specific
application, please consult the Total Endurance? Model which can be downloaded at www.microchip.com.
FIGURE 1-2:
BUS TIMING DATA
SCL
T F
T LOW
T HIGH
T R
SDA
IN
T SU : STA
T SP
T HD : STA
T HD : DAT
T SU : DAT
T SU : STO
T BUF
SDA
OUT
DS21073K-page 4
T AA
T AA
? 2008 Microchip Technology Inc.
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