参数资料
| 型号： | 24FC1025-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 5/28页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 1MBIT 1MHZ 8SOIC |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 1M (128K x 8) |
| 速度： | 400kHz，1MHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 管件 |
第1页第2页第3页第4页当前第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
24AA1025/24LC1025/24FC1025
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1 .
TABLE 2-1:
PIN FUNCTION TABLE
Name
A0
A1
A2
PDIP
1
2
3
SOIJ
1
2
3
SOIC
1
2
3
Function
User Configurable Chip Select
User Configurable Chip Select
Non-Configurable Chip Select.
This pin must be hard-wired to logical 1 state (V CC ). Operation will
be undefined with this pin left floating or held to logical 0 (V SS ).
V SS
SDA
SCL
WP
V CC
4
5
6
7
8
4
5
6
7
8
4
5
6
7
8
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.7 to 5.5V (24AA1025)
+2.5 to 5.5V (24LC1025)
+1.8 to 5.5V (24FC1025)
2.1
A0, A1 Chip Address Inputs
2.3
Serial Data (SDA)
The A0 and A1 inputs are used by the 24XX1025 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A0 and A1 are
hard-wired to logic ‘ 0 ’ or logic ‘ 1 ’. For applications in
which these pins are controlled by a microcontroller or
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pull-
up resistor to V CC (typical 10 k ? for 100 kHz, 2 k ?? for
400 kHz and 1 MHz).
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
other programmable device, the chip address pins
must be driven to logic ‘ 0 ’ or logic ‘ 1 ’ before normal
2.4
Serial Clock (SCL)
device operation can proceed.
This input is used to synchronize the data transfer from
and to the device.
2.2
A2 Chip Address Input
2.5
Write-Protect (WP)
The A2 input is non-configurable Chip Select. This pin
must be tied to V CC in order for this device to operate.
If left floating or tied to V SS , device operation will be
undefined.
? 2005-2012 Microchip Technology Inc.
This pin must be connected to either V SS or V CC . If tied
to V SS , write operations are enabled. If tied to V CC ,
write operations are inhibited, but read operations are
not affected.
DS21941K-page 5
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