参数资料
| 型号： | 24FC128-I/ST |
| 厂商： | Microchip Technology |
| 文件页数： | 6/38页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 128KBIT 1MHZ 8TSSOP |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 128K (16K x 8) |
| 速度： | 400kHz，1MHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 1447 (CN2011-ZH PDF) |
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24AA128/24LC128/24FC128
4.0 BUS CHARACTERISTICS
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
is not busy.
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device.
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
4.5
Acknowledge
Accordingly, the following bus conditions have been
defined (Figure 4-1).
Each receiving device, when addressed, is obliged to
generate an Acknowledge signal after the reception of
4.1
Bus Not Busy (A)
each byte. The master device must generate an extra
clock pulse, which is associated with this Acknowledge
Both data and clock lines remain high.
bit.
4.2
Start Data Transfer (B)
Note:
The 24XX128 does not generate any
Acknowledge bits if an internal
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
programming cycle is in progress.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
4.3
Stop Data Transfer (C)
that the SDA line is stable low during the high period of
the acknowledge related clock pulse. Of course, setup
A low-to-high transition of the SDA line, while the clock
(SCL) is high, determines a Stop condition. All
operations must end with a Stop condition.
4.4 Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
and hold times must be taken into account. During
reads, a master must signal an end of data to the slave
by NOT generating an Acknowledge bit on the last byte
that has been clocked out of the slave. In this case, the
slave (24XX128) will leave the data line high to enable
the master to generate the Stop condition.
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS
(A)
(B)
(D)
(D)
(C)
(A)
SCL
SDA
Start
Condition
FIGURE 4-2:
Address or
Acknowledge
Valid
ACKNOWLEDGE TIMING
Data
Allowed
to Change
Stop
Condition
Acknowledge
Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter
Data from transmitter
Transmitter must release the SDA line at this point,
allowing the Receiver to pull the SDA line low to
acknowledge the previous eight bits of data.
DS21191S-page 6
Receiver must release the SDA line
at this point so the Transmitter can
continue sending data.
? 2010 Microchip Technology Inc.
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