参数资料
| 型号： | 24FC128-I/ST |
| 厂商： | Microchip Technology |
| 文件页数： | 7/38页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 128KBIT 1MHZ 8TSSOP |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 100 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 128K (16K x 8) |
| 速度： | 400kHz，1MHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 1.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 管件 |
| 产品目录页面： | 1447 (CN2011-ZH PDF) |
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24AA128/24LC128/24FC128
5.0 DEVICE ADDRESSING
A control byte is the first byte received following the
Start condition from the master device (Figure 5-1).
The control byte consists of a 4-bit control code. For the
FIGURE 5-1:
CONTROL BYTE
FORMAT
Read/Write Bit
24XX128, this is set as ‘ 1010 ’ binary for read and write
operations. The next three bits of the control byte are
the Chip Select bits (A2, A1, A0). The Chip Select bits
Control Code
Chip Select
Bits
allow the use of up to eight 24XX128 devices on the
same bus and are used to select which device is
S
1
0
1
0
A2
A1
A0 R/W ACK
accessed. The Chip Select bits in the control byte must
correspond to the logic levels on the corresponding A2,
Slave Address
A1 and A0 pins for the device to respond. These bits
are, in effect, the three Most Significant bits of the word
address.
For the MSOP package, the A0 and A1 pins are not
connected. During device addressing, the A0 and A1
Start Bit
5.1
Acknowledge Bit
Contiguous Addressing Across
Multiple Devices
Chip Select bits (Figures 5-1 and 5-2) should be set to
‘ 0 ’. Only two 24XX128 MSOP packages can be
connected to the same bus.
The last bit of the control byte defines the operation to
be performed. When set to a one, a read operation is
selected. When set to a zero, a write operation is
selected. The next two bytes received define the
address of the first data byte (Figure 5-2). Because
only A13…A0 are used, the upper two address bits are
“don’t care” bits. The upper address bits are transferred
first, followed by the Less Significant bits.
Following the Start condition, the 24XX128 monitors
the SDA bus checking the device type identifier being
transmitted. Upon receiving a ‘ 1010 ’ code and
appropriate device select bits, the slave device outputs
an Acknowledge signal on the SDA line. Depending on
the state of the R/W bit, the 24XX128 will select a read
or write operation.
The Chip Select bits A2, A1 and A0 can be used to
expand the contiguous address space for up to 1 Mbit
by adding up to eight 24XX128 devices on the same
bus. In this case, software can use A0 of the control
byte as address bit A14; A1 as address bit A15; and A2
as address bit A16. It is not possible to sequentially
read across device boundaries.
For the MSOP package, up to two 24XX128 devices
can be added for up to 256 Kbit of address space. In
this case, software can use A2 of the control byte as
address bit A16. Bits A0 (A14) and A1 (A15) of the
control byte must always be set to logic ‘ 0 ’ for the
MSOP.
FIGURE 5-2:
ADDRESS SEQUENCE BIT ASSIGNMENTS
Control Byte
Address High Byte
Address Low Byte
0 R/W
1
0
1
0
A
2
A
1
A
x
x
A A A A
13 12 11 10
A
9
A
8
A
7
?
?
?
?
?
?
A
0
Control
Code
Chip
Select
Bits
x = “don’t care” bit
? 2010 Microchip Technology Inc.
DS21191S-page 7
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