参数资料
| 型号： | 24LC025T/ST |
| 厂商： | Microchip Technology |
| 文件页数： | 6/30页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 400KHZ 8TSSOP |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 2,500 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 400kHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | 0°C ~ 70°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
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24AA024/24LC024/24AA025/24LC025
4.0
BUS CHARACTERISTICS
The data on the line must be changed during the low
period of the clock signal. There is one bit of data per
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
is not busy.
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined (Figure 4-1).
clock pulse.
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of the
data bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited (though only the last sixteen will
be stored when performing a write operation). When an
overwrite does occur, it will replace data in a first-in
first-out fashion.
4.1
Bus Not Busy (A)
4.5
Acknowledge
Both data and clock lines remain high.
Each receiving device, when addressed, is required to
generate an acknowledge after the reception of each
4.2
Start Data Transfer (B)
byte. The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
Note:
The 24AA024/24LC024/24AA025/24LC025
does not generate any Acknowledge bits if
an internal programming cycle is in prog-
4.3
Stop Data Transfer (C)
ress.
The device that acknowledges has to pull down the SDA
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
line during the acknowledge clock pulse in such a way
that the SDA line is stable low during the high period of
the acknowledge-related clock pulse. Of course, setup
and hold times must be taken into account. A master
4.4
Data Valid (D)
must signal an end of data to the slave by not generating
an Acknowledge bit on the last byte that has been
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
clocked out of the slave. In this case, the slave must
leave the data line high to enable the master to generate
the Stop condition (Figure 4-2).
FIGURE 4-1:
DATA TRANSFER SEQUENCE ON THE SERIAL BUS CHARACTERISTICS
SCL
(A)
(B)
(C)
(D)
(C)
(A)
SDA
Start
Condition
FIGURE 4-2:
Address or
Acknowledge
Valid
ACKNOWLEDGE TIMING
Data
Allowed
to Change
Stop
Condition
Acknowledge
Bit
SCL
1
2
3
4
5
6
7
8
9
1
2
3
SDA
Data from transmitter
Data from transmitter
Transmitter must release the SDA line at this point allowing
the Receiver to pull the SDA line low to acknowledge the
previous eight bits of data.
DS21210N-page 6
Receiver must release the SDA line at this
point so the Transmitter can continue
sending data.
? 2009 Microchip Technology Inc.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 24LC028IP | 制造商:Microchip Technology Inc 功能描述: |
| 24LC02AIP | 制造商:Panasonic Industrial Company 功能描述:SUB ONLY IC |
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| 24LC02B/MS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:EEPROM |
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