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参数资料
| 型号： | 24LC08B/P |
| 元件分类： | PROM |
| 英文描述： | 1K X 8 I2C/2-WIRE SERIAL EEPROM, PDIP8 |
| 封装： | 0.300 INCH, PLASTIC, DIP-8 |
| 文件页数： | 15/20页 |
| 文件大小： | 355K |
| 代理商： | 24LC08B/P |
24LC04B/08B
DS21051H-page 4
2001 Microchip Technology Inc.
FIGURE 1-2:
BUS TIMING DATA
2.0
FUNCTIONAL DESCRIPTION
The 24LC04B/08B supports a bi-directional 2-wire bus
and data transmission protocol. A device that sends
data onto the bus is defined as transmitter and if receiv-
ing data, as receiver. The bus has to be controlled by a
master device which generates the serial clock (SCL),
controls the bus access and generates the START and
STOP conditions, while the 24LC04B/08B works as
slave. Both master and slave can operate as transmit-
ter or receiver, but the master device determines which
mode is activated.
3.0
BUS CHARACTERISTICS
The following bus protocol has been defined:
Data transfer may be initiated only when the bus
is not busy
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition
Accordingly, the following bus conditions have been
defined (Figure 3-1).
3.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
3.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition. All
commands must be preceded by a START condition.
3.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must be ended with a STOP condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one clock pulse per
bit of data.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device
and is theoretically unlimited, although only the last 16
will be stored when doing a write operation. When an
overwrite does occur it will replace data in a first in first
out fashion.
3.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge after the reception of each
byte. The master device must generate an extra clock
pulse which is associated with this acknowledge bit.
The device that acknowledges, has to pull down the
SDA line during the acknowledge clock pulse in such a
way that the SDA line is stable LOW during the HIGH
period of the acknowledge related clock pulse.
Of
course, setup and hold times must be taken into
account. A master must signal an end of data to the
slave by not generating an acknowledge bit on the last
byte that has been clocked out of the slave. In this
case, the slave must leave the data line HIGH to enable
the master to generate the STOP condition.
TSU:STA
TF
TLOW
THIGH
TR
THD:DAT
TSU:DAT
TSU:STO
THD:STA
TBUF
TAA
TSP
THD:STA
SCL
SDA
IN
SDA
OUT
Note:
The 24LC04B/08B does not generate
any acknowledge bits if an internal pro-
gramming cycle is in progress.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 24LC08BSN | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K I2Ca?￠ Serial EEPROM |
| 24LC08BT | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:8K I2C? Serial EEPROM |
| 24LC08BT-/SL | 制造商:未知厂家 制造商全称:未知厂家 功能描述:I2C Serial EEPROM |
| 24LC08BT-/SM | 制造商:未知厂家 制造商全称:未知厂家 功能描述:I2C Serial EEPROM |
| 24LC08BT/SN | 功能描述:电可擦除可编程只读存储器 1kx8 - 2.5V RoHS:否 制造商:Atmel 存储容量:2 Kbit 组织:256 B x 8 数据保留:100 yr 最大时钟频率:1000 KHz 最大工作电流:6 uA 工作电源电压:1.7 V to 5.5 V 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-8 |
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