参数资料
型号: 24LC128ESN
厂商: Microchip Technology Inc.
元件分类: EEPROM
英文描述: The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
中文描述: 该CAT24FC02是一个2 KB的EEPROM的国内256个8位每字举办的串行CMOS
文件页数: 6/12页
文件大小: 185K
代理商: 24LC128ESN
1998 Microchip Technology Inc.
DS21191B-page 3
24AA128/24LC128
TABLE 1-3
AC CHARACTERISTICS
All parameters apply across the spec-
ied operating ranges unless other-
wise noted.
Industrial (I):
VCC = +1.8V to 5.5V
Tamb = -40
°C to +85°C
Automotive (E): VCC = +4.5V to 5.5V
Tamb = -40
°C to 125°C
Parameter
Symbol
Min
Max
Units
Conditions
Clock frequency
FCLK
100
400
kHz
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
Clock high time
THIGH
4000
600
ns
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
Clock low time
TLOW
4700
1300
ns
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
SDA and SCL rise time
TR
1000
300
ns
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
SDA and SCL fall time
TF
300
ns
START condition hold time
THD:STA
4000
600
ns
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
START condition setup time
TSU:STA
4700
600
ns
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
Data input hold time
THD:DAT
0
ns
Data input setup time
TSU:DAT
250
100
ns
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
STOP condition setup time
TSU:STO
4000
600
ns
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
WP setup time
TSU:WP
4000
600
ns
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
WP hold time
THD:WP
4700
1300
ns
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
Output valid from clock
TAA
3500
900
ns
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
Bus free time: Time the bus must be
free before a new transmission can
start
TBUF
4700
1300
ns
4.5V
≤ VCC ≤ 5.5V (E Temp range)
1.8V
≤ VCC ≤ 2.5V
2.5V
≤ VCC ≤ 5.5V
Output fall time from VIH
minimum to VIL maximum
TOF
10
250
ns
CB ≤ 100 pF (Note 1)
Input lter spike suppression
(SDA and SCL pins)
TSP
50
ns
Write cycle time (byte or page)
TWC
—5
ms
Endurance
1M
cycles
25
°C, VCC = 5.0V, Block Mode (Note 4)
Note 1:
Not 100% tested. CB = total capacitance of one bus line in pF.
2:
As a transmitter, the device must provide an internal minimum delay time to bridge the undened region (minimum
300 ns) of the falling edge of SCL to avoid unintended generation of START or STOP conditions.
3:
The combined TSP and VHYS specications are due to new Schmitt trigger inputs which provide improved noise spike
suppression. This eliminates the need for a TI specication for standard operation.
4:
This parameter is not tested but guaranteed by characterization. For endurance estimates in a specic application, please
consult the Total Endurance Model which can be obtained on Microchip’s BBS or website.
相关PDF资料
PDF描述
24LC128EST The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
24LC128IP The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
24LC128ISM The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
24LC128ISN The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
24LC128IST The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each
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