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参数资料
| 型号： | 24LC128ESN |
| 厂商： | Microchip Technology Inc. |
| 元件分类： | EEPROM |
| 英文描述： | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 中文描述： | 该CAT24FC02是一个2 KB的EEPROM的国内256个8位每字举办的串行CMOS |
| 文件页数： | 7/12页 |
| 文件大小： | 185K |
| 代理商： | 24LC128ESN |
24AA128/24LC128
DS21191B-page 4
1998 Microchip Technology Inc.
2.0
PIN DESCRIPTIONS
2.1
A0, A1, A2 Chip Address Inputs
The A0, A1, A2 inputs are used by the 24xx128 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight devices may be connected to the same bus
by using different chip select bit combinations. If left
unconnected, these inputs will be pulled down inter-
nally to VSS.
2.2
SDA Serial Data
This is a bi-directional pin used to transfer addresses
and data into and data out of the device. It is an open-
drain terminal, therefore, the SDA bus requires a pullup
resistor to VCC (typical 10 k
for 100 kHz, 2 k for
400 kHz)
For normal data transfer SDA is allowed to change only
during SCL low. Changes during SCL high are
reserved for indicating the START and STOP condi-
tions.
2.3
SCL Serial Clock
This input is used to synchronize the data transfer from
and to the device.
2.4
WP
This pin can be connected to either VSS, VCC or left
oating. An internal pull-down resistor on this pin will
keep the device in the unprotected state if left oating.
If tied to VSS or left oating, normal memory operation
is enabled (read/write the entire memory 0000-3FFF).
If tied to VCC, WRITE operations are inhibited. Read
operations are not affected.
3.0
FUNCTIONAL DESCRIPTION
The 24xx128 supports a bi-directional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is dened as a transmitter, and a device
receiving data as a receiver. The bus must be con-
trolled by a master device which generates the serial
clock (SCL), controls the bus access, and generates
the START and STOP conditions while the 24xx128
works as a slave. Both master and slave can operate as
a transmitter or receiver, but the master device deter-
mines which mode is activated.
4.0
BUS CHARACTERISTICS
The following bus protocol has been dened:
Data transfer may be initiated only when the bus
is not busy.
During data transfer, the data line must remain
stable whenever the clock line is HIGH. Changes
in the data line while the clock line is HIGH will be
interpreted as a START or STOP condition.
Accordingly, the following bus conditions have been
dened (Figure 4-1).
4.1
Bus not Busy (A)
Both data and clock lines remain HIGH.
4.2
Start Data Transfer (B)
A HIGH to LOW transition of the SDA line while the
clock (SCL) is HIGH determines a START condition.
All commands must be preceded by a START condi-
tion.
4.3
Stop Data Transfer (C)
A LOW to HIGH transition of the SDA line while the
clock (SCL) is HIGH determines a STOP condition. All
operations must end with a STOP condition.
4.4
Data Valid (D)
The state of the data line represents valid data when,
after a START condition, the data line is stable for the
duration of the HIGH period of the clock signal.
The data on the line must be changed during the LOW
period of the clock signal. There is one bit of data per
clock pulse.
Each data transfer is initiated with a START condition
and terminated with a STOP condition. The number of
the data bytes transferred between the START and
STOP conditions is determined by the master device.
4.5
Acknowledge
Each receiving device, when addressed, is obliged to
generate an acknowledge signal after the reception of
each byte. The master device must generate an extra
clock pulse which is associated with this acknowledge
bit.
A device that acknowledges must pull down the SDA
line during the acknowledge clock pulse in such a way
that the SDA line is stable LOW during the HIGH period
of the acknowledge related clock pulse. Of course,
setup and hold times must be taken into account. Dur-
ing reads, a master must signal an end of data to the
slave by NOT generating an acknowledge bit on the
last byte that has been clocked out of the slave. In this
case, the slave (24xx128) will leave the data line HIGH
to enable the master to generate the STOP condition.
Note:
The 24xx128 does not generate any
acknowledge bits if an internal program-
ming cycle is in progress.
相关PDF资料 |
PDF描述 |
|---|---|
| 24LC128EST | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 24LC128IP | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 24LC128ISM | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 24LC128ISN | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
| 24LC128IST | The CAT24FC02 is a 2-kb Serial CMOS EEPROM internally organized as 256 words of 8 bits each |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 24LC128-ESN | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:I2C⑩ Serial EEPROM Family Data Sheet |
| 24LC128EST | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:128K I 2 C ⑩ CMOS Serial EEPROM |
| 24LC128-EST | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:I2C⑩ Serial EEPROM Family Data Sheet |
| 24LC128-I/CS15K | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:128K I2C? CMOS Serial EEPROM |
| 24LC128-I/MC | 制造商:MICROCHIP 制造商全称:Microchip Technology 功能描述:I2C⑩ Serial EEPROM Family Data Sheet |
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