参数资料
型号: 24VL014/P
厂商: Microchip Technology
文件页数: 5/30页
文件大小: 0K
描述: IC EEPROM 1KBIT 400KHZ 8DIP
标准包装: 60
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 1K (128 x 8)
速度: 100kHz,400kHz
接口: I²C,2 线串口
电源电压: 1.5 V ~ 3.6 V
工作温度: -20°C ~ 85°C
封装/外壳: 8-DIP(0.300",7.62mm)
供应商设备封装: 8-PDIP
包装: 管件
产品目录页面: 1443 (CN2011-ZH PDF)
24VL014
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Name
A0
A1
A2
V SS
SDA
SCL
WP
V CC
8-pin
PDIP
1
2
3
4
5
6
7
8
8-pin
SOIC
1
2
3
4
5
6
7
8
8-pin
TSSOP
1
2
3
4
5
6
7
8
8-pin
MSOP
1
2
3
4
5
6
7
8
8-pin
TDFN
1
2
3
4
5
6
7
8
6-pin
SOT-23
5
4
2
3
1
6
Function
User Configurable Chip Select
User Configurable Chip Select
User Configurable Chip Select
Ground
Serial Data
Serial Clock
Write-Protect Input
+1.5V to 3.6V
2.1
SDA Serial Data
2.5
Noise Protection
This is a bidirectional pin used to transfer addresses
and data into and out of the device. It is an open drain
terminal. Therefore, the SDA bus requires a pull-up
resistor to V CC (typical 10 k Ω for 100 kHz, 2 k Ω for
400 kHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
The 24VL014 employs a V CC threshold detector circuit
that disables the internal erase/write logic if the V CC is
below 1.0 volts at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits that suppress noise spikes to assure
proper device operation even on a noisy bus.
2.2
SCL Serial Clock
The SCL input is used to synchronize the data transfer
to and from the device.
2.3
A0, A1, A2
The A0, A1 and A2 inputs are used by the 24VL014 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the compare is true.
Up to eight 24VL014 devices (four for the SOT-23
package) may be connected to the same bus by using
different Chip Select bit combinations. These inputs
must be connected to either V CC or V SS .
In most applications, the chip address inputs A0, A1
and A2 are hard-wired to logic ‘ 0 ’ or logic ‘ 1 ’. For
applications in which these pins are controlled by a
microcontroller or other programmable device, the chip
address pins must be driven to logic ‘ 0 ’ or logic ‘ 1 ’
before normal device operation can proceed.
2.4
WP
WP is the hardware write-protect pin. It must be tied to
V CC or V SS . If tied to V CC , the hardware write protection
is enabled and will protect the entire array (00h-7Fh). If
the WP pin is tied to V SS the hardware write protection
is disabled. Write Protection is not available on the
SOT-23 package; for this package, write operations are
always enabled.
? 2009 Microchip Technology Inc.
DS22129A-page 5
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