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参数资料
| 型号： | 25AA02E48T-I/OT |
| 厂商： | Microchip Technology |
| 文件页数： | 14/26页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 10MHZ SOT23-6 |
| 产品培训模块： | MAC Address EEPROMs |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROM - 串行（带 MAC 地址） |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 10MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-23-6 |
| 包装： | 标准包装 |
| 产品目录页面： | 1448 (CN2011-ZH PDF) |
| 其它名称： | 25AA02E48T-I/OTDKR |
25AA02E48
4.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 4-1.
4.5
Serial Clock (SCK)
TABLE 4-1:
PIN FUNCTION TABLE
The SCK is used to synchronize the communication
between a master and the 25AA02E48. Instructions,
Name
CS
SO
SOIC
1
2
SOT-23
5
4
Function
Chip Select Input
Serial Data Output
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
WP
3
—
Write-Protect Pin
4.6
Hold (HOLD)
V SS
SI
SCK
HOLD
V CC
4
5
6
7
8
2
3
1
—
6
Ground
Serial Data Input
Serial Clock Input
Hold Input
Supply Voltage
The HOLD pin is used to suspend transmission to the
25AA02E48 while in the middle of a serial sequence
without having to retransmit the entire sequence again.
It must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
4.1
Chip Select (CS)
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
program cycle, the device will go into Standby mode as
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
being initiated.
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25AA02E48 must remain selected
during this sequence. The SI, SCK and SO pins are in
a high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
4.2
Serial Output (SO)
The SO pin is used to transfer data out of the
25AA02E48. During a read cycle, data is shifted out on
this pin after the falling edge of the serial clock.
4.3
Write-Protect (WP)
The WP pin is a hardware write-protect input pin.
When it is low, all writes to the array or STATUS reg-
ister are disabled, but any other operations function
normally. When WP is high, all functions, including
nonvolatile writes operate normally. At any time, when
WP is low, the write enable Reset latch will be reset
and programming will be inhibited. However, if a write
cycle is already in progress, WP going low will not
change or disable the write cycle. See Table 2-4 for
the Write-Protect Functionality Matrix.
4.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
DS22123B-page 14
? 2010 Microchip Technology Inc.
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