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| 型号： | 25AA02E48T-I/OT |
| 厂商： | Microchip Technology |
| 文件页数： | 6/26页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 10MHZ SOT23-6 |
| 产品培训模块： | MAC Address EEPROMs |
| 标准包装： | 1 |
| 格式 - 存储器： | EEPROM - 串行（带 MAC 地址） |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 10MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | SOT-23-6 |
| 供应商设备封装： | SOT-23-6 |
| 包装： | 标准包装 |
| 产品目录页面： | 1448 (CN2011-ZH PDF) |
| 其它名称： | 25AA02E48T-I/OTDKR |
25AA02E48
2.0
2.1
FUNCTIONAL DESCRIPTION
Principles of Operation
After setting the write enable latch, the user may
proceed by driving CS low, issuing a WRITE instruction,
followed by the remainder of the address, and then the
data to be written. Up to 16 bytes of data can be sent to
The 25AA02E48 is a 256-byte Serial EEPROM
designed to interface directly with the Serial Peripheral
Interface (SPI) port of many of today’s popular
microcontroller families, including Microchip’s PIC ?
microcontrollers. It may also interface with microcon-
trollers that do not have a built-in SPI port by using
discrete I/O lines programmed properly in software to
match the SPI protocol.
The 25AA02E48 contains an 8-bit instruction register.
the device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page. Additionally, a page address begins with
XXXX 0000 and ends with XXXX 1111 . If the internal
address counter reaches XXXX 1111 and clock signals
continue to be applied to the chip, the address counter
will roll back to the first address of the page and over-
write any data that previously existed in those
locations.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low and the HOLD pin must be high for the entire
operation.
Table 2-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses, and data are transferred MSb first, LSb last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low. If the clock line is shared with other
peripheral devices on the SPI bus, the user can assert
the HOLD input and place the 25AA02E48 in ‘HOLD’
mode. After releasing the HOLD pin, operation will
resume from the point when the HOLD was asserted.
Note:
Page write operations are limited to writing
bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size (or
‘page size’) and, end at addresses that are
integer multiples of page size – 1. If a
Page Write command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
2.2
Read Sequence
expected. It is therefore necessary for the
application software to prevent page write
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the 25AA02E48
followed by an 8-bit address. See Figure 2-1 for more
details.
After the correct READ instruction and address are sent,
the data stored in the memory at the selected address
is shifted out on the SO pin. Data stored in the memory
at the next address can be read sequentially by
continuing to provide clock pulses to the slave. The
internal Address Pointer automatically increments to
the next higher address after each byte of data is
shifted out. When the highest address is reached
(FFh), the address counter rolls over to address 00h
allowing the read cycle to be continued indefinitely. The
read operation is terminated by raising the CS pin
(Figure 2-1).
operations that would attempt to cross a
page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the n th data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 2-2 and Figure 2-3 for more
detailed illustrations on the byte write sequence and
the page write sequence respectively. While the write is
in progress, the STATUS register may be read to check
the status of the WIP, WEL, BP1 and BP0 bits
(Figure 2-6). Attempting to read a memory array
location will not be possible during a write cycle. Polling
the WIP bit in the STATUS register is recommended in
order to determine if a write cycle is in progress. When
the write cycle is completed, the write enable latch is
reset.
2.3
Write Sequence
Prior to any attempt to write data to the 25AA02E48,
the write enable latch must be set by issuing the WREN
instruction (Figure 2-4). This is done by setting CS low
and then clocking out the proper instruction into the
25AA02E48. After all eight bits of the instruction are
transmitted, CS must be driven high to set the write
enable latch. If the write operation is initiated immedi-
ately after the WREN instruction without CS driven high,
data will not be written to the array since the write
enable latch was not properly set.
DS22123B-page 6
? 2010 Microchip Technology Inc.
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