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参数资料
| 型号： | 25AA320XT-I/ST |
| 厂商： | Microchip Technology |
| 文件页数： | 6/26页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 32KBIT 1MHZ 8TSSOP |
| 标准包装： | 2,500 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 32K (4K x 8) |
| 速度： | 1MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 1.8 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
| 其它名称： | 25AA320XTI/ST |
25AA320/25LC320/25C320
2.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1:
PIN FUNCTION TABLE
Name
CS
SO
NC
WP
Vss
SI
SCK
NC
HOLD
Vcc
PDIP
1
2
—
3
4
5
6
—
7
8
SOIC
1
2
—
3
4
5
6
—
7
8
8-pin
TSSOP
3
4
—
5
6
7
8
—
1
2
14-lead
TSSOP
1
2
3,4,5
6
7
8
9
10,11,12
13
14
Description
Chip Select Input
Serial Data Output
Not Connected
Write-Protect Pin
Ground
Serial Data Input
Serial Clock Input
Not Connected
Hold Input
Supply Voltage
2.1
Chip Select (CS)
The WP pin function is blocked when the WPEN bit in
A low level on this pin selects the device. A high level
deselects the device and forces it into Standby mode.
However, a programming cycle which is already
initiated or in progress will be completed, regardless of
the CS input signal. If CS is brought high during a
the STATUS register is low. This allows the user to
install the 25XX320 in a system with WP pin grounded
and still be able to write to the STATUS register. The
WP pin functions will be enabled when the WPEN bit is
set high.
program cycle, the device will go into Standby mode as
2.4
Serial Input (SI)
soon as the programming cycle is complete. When the
device is deselected, SO goes to the high-impedance
state, allowing multiple parts to share the same SPI
bus. A low-to-high transition on CS after a valid write
The SI pin is used to transfer data into the device. It
receives instructions, addresses, and data. Data is
latched on the rising edge of the serial clock.
sequence initiates an internal write cycle. After power-
up, a low level on CS is required prior to any sequence
2.5
Serial Clock (SCK)
being initiated.
The SCK is used to synchronize the communication
between a master and the 25XX320. Instructions,
2.2
Serial Output (SO)
addresses, or data present on the SI pin are latched on
The SO pin is used to transfer data out of the 25XX320.
During a read cycle, data is shifted out on this pin after
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
the falling edge of the serial clock.
2.6
Hold (HOLD)
2.3
Write-Protect (WP)
The HOLD pin is used to suspend transmission to the
This pin is used in conjunction with the WPEN bit in the
STATUS register to prohibit writes to the nonvolatile
bits in the STATUS register. When WP is low and
WPEN is high, writing to the nonvolatile bits in the STA-
TUS register is disabled. All other operations function
normally. When WP is high, all functions, including
writes to the nonvolatile bits in the STATUS register
operate normally. If the WPEN bit is set, WP low during
a STATUS register write sequence will disable writing
to the STATUS register. If an internal write cycle has
already begun, WP going low will have no effect on the
write.
DS21227F-page 6
25XX320 while in the middle of a serial sequence with-
out having to re-transmit the entire sequence again. It
must be held high any time this function is not being
used. Once the device is selected and a serial
sequence is underway, the HOLD pin may be pulled
low to pause further serial communication without
resetting the serial sequence. The HOLD pin must be
brought low while SCK is low, otherwise the HOLD
function will not be invoked until the next SCK high-to-
low transition. The 25XX320 must remain selected dur-
ing this sequence. The SI, SCK, and SO pins are in a
high-impedance state during the time the device is
paused and transitions on these pins will be ignored. To
resume serial communication, HOLD must be brought
high while the SCK pin is low, otherwise serial
communication will not resume. Lowering the HOLD
line at any time will tri-state the SO line.
? 2008 Microchip Technology Inc.
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