参数资料
型号: 25LC128T-I/MF
厂商: Microchip Technology
文件页数: 11/32页
文件大小: 0K
描述: IC EEPROM 128KBIT 10MHZ 8DFN
标准包装: 3,300
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 128K (16K x 8)
速度: 10MHz
接口: SPI 3 线串行
电源电压: 2.5 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 8-VDFN 裸露焊盘
供应商设备封装: 8-DFN-S(6x5)
包装: 带卷 (TR)
其它名称: 25LC128T-I/MFTR
25AA128/25LC128
2.6
Write Status Register (WRSR)
The Write Status Register ( WRSR ) instruction allows the
user to write to the nonvolatile bits in the STATUS reg-
ister as shown in Table 2-2. The user is able to select
one of four levels of protection for the array by writing
to the appropriate bits in the STATUS register. The
only writes to nonvolatile bits in the STATUS register
are disabled. See Table 2-4 for a matrix of functionality
on the WPEN bit.
See Figure 2-7 for the WRSR timing sequence.
array is divided up into four segments. The user has the
ability to write-protect none, one, two, or all four of the
TABLE 2-3:
ARRAY PROTECTION
segments of the array. The partitioning is controlled as
shown in Table 2-3.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the
programmable hardware write-protect feature. Hard-
ware write protection is enabled when WP pin is low
and the WPEN bit is high. Hardware write protection is
disabled when either the WP pin is high or the WPEN
bit is low. When the chip is hardware write-protected,
BP1
0
0
1
1
BP0
0
1
0
1
Array Addresses
Write-Protected
none
upper 1/4
(3000h-3FFFh)
upper 1/2
(2000h-3FFFh)
all
(0000h-3FFFh)
FIGURE 2-7:
CS
WRITE STATUS REGISTER TIMING SEQUENCE ( WRSR )
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction
Data to STATUS Register
SI
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
High-Impedance
SO
Note:
An internal write cycle (T WC ) is initiated on the rising edge of CS after a valid write STATUS register
? 2003-2011 Microchip Technology Inc.
DS21831E-page 11
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