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参数资料
| 型号： | 25LC640XT-I/ST |
| 厂商： | Microchip Technology |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 64KBIT 2MHZ 8TSSOP |
| 标准包装： | 2,500 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 64K (8K x 8) |
| 速度： | 2MHz |
| 接口： | SPI 3 线串行 |
| 电源电压： | 2.5 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 8-TSSOP |
| 包装： | 带卷 (TR) |
25AA640/25LC640
3.6
Write Status Register Instruction
TABLE 3-2:
ARRAY PROTECTION
( WRSR )
The Write Status Register instruction ( WRSR ) allows the
user to select one of four levels of protection for the
array by writing to the appropriate bits in the STATUS
register. The array is divided up into four segments.
The user has the ability to write-protect none, one, two,
or all four of the segments of the array. The partitioning
is controlled as shown in Table 3-2.
The Write-Protect Enable (WPEN) bit is a nonvolatile
bit that is available as an enable bit for the WP pin. The
BP1
0
0
1
1
BP0
0
1
0
1
Array Addresses
Write-Protected
none
upper 1/4
(1800h-1FFFh)
upper 1/2
(1000h-1FFFh)
all
(0000h-1FFFh)
Write-Protect (WP) pin and the Write-Protect Enable
(WPEN) bit in the STATUS register control the pro-
grammable hardware write-protect feature. Hardware
write protection is enabled when the WP pin is low and
the WPEN bit is high. Hardware write protection is dis-
abled when either the WP pin is high or the WPEN bit
is low. When the chip is hardware write-protected, only
writes to nonvolatile bits in the STATUS register are dis-
abled. See Table 3-3 for a matrix of functionality on the
WPEN bit.
See Figure 3-7 for WRSR timing sequence.
FIGURE 3-7:
CS
WRITE STATUS REGISTER TIMING SEQUENCE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction
Data to STATUS Register
SI
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
High-Impedance
SO
? 2008 Microchip Technology Inc.
DS21223H-page 11
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