28229-DSH-001-B
Mindspeed Technologies
7
-7
CX28224/5/9 Data Sheet
Registers
Table 7-10 lists IMA control and status information.
0x39
RXCNTM
Received Cell Counter [Mid Byte]
0x3A
RXCNTH
Received Cell Counter [High Byte]
0x3C
NONCNTL
Non-matching Cell Counter [Low Byte]
0x3D
NONCNTH
Non-matching Cell Counter [High Byte]
Table 7-10. IMA Control and Status Registers (1 of 26)
Address
Name
Description
Page
Number
0x400
IMA_VER_1_CONFIG
Device Version I
0x401
IMA_VER_2_CONFIG
Device Version II
0x402
IMA_SUBSYS_CONFIG
Configuration Control
0x403
IMA_MISC_STATUS
Miscellaneous Status
0x404
IMA_MISC_CONFIG
Miscellaneous Control
0x405
IMA_MEM_LOW_TEST
Memory Test Address
0x406
IMA_MEM_HI_TEST
Memory Test Address
0x407
IMA_MEM_TEST_CTL
Memory Test Control
0x408
IMA_MEM_TEST_DATA
Memory Test Data
0x409
IMA_LNK_DIAG_CTL
Link Diagnostic Control
0x40a
IMA_LNK_DIFF_DEL
Link Differential Delay
0x40b
IMA_RCV_LNK_ANOMALIES
Receive Link Anomalies
0x40e
IMA_DIAG_XOR_BIT
Address Diagnostic
0x40f
IMA_DIAG
Diagnostic Register
0x410
IMA_TIM_REF_MUX_CTL_ADDR
TRL Control Address
0x411
IMA_TIM_REF_MUX_CTL_DATA
TRL Control Data
0x412
IMA_RX_PERSIST_CONFIG
Receive Persistence
0x413
IMA_ATM_UTOPIA_BUS_CTL
ATM Utopia Control
0x414
IMA_DIFF_DELAY_ADDR
Diff. Delay Control Address
0x415
IMA_DIFF_DELAY_DATA
Diff. Delay Control Data
0x416
IMA_DSL_CLOCK_GEN_ADDR
DSL Clock Generator Control Address
0x417
IMA_DSL_CLOCK_GEN_DATA
DSL Clock Generator Control Data
0x418
IMA_RX_TRANS_TABLE
Receive Translation Table Address
0x419
IMA_RX_ATM_TRANS_TABLE
Receive Translation Table Internal Channel
0x41b
IMA_TX_TRANS_TABLE
Transmit Translation Table Address
Table 7-9. Counters (2 of 2)
Port Offset
Address
Name
Description (Continued)
Page
Number