7-6
Mindspeed Technologies
28229-DSH-001-B
Registers
CX28224/5/9 Data Sheet
Table 7-7 lists the control registers for the UTOPIA operations.
Table 7-8 lists interrupt enables, interrupt indications, and status information.
Table 7-9 lists the CX2822x’s counters. When the counters fill, they saturate and do
not roll over. The counts have been sized to ensure against saturation within a one-
second interval. Therefore, when one-second latching is enabled, the counters are read
and cleared before they can saturate. All counters are cleared when read.
Table 7-7. UTOPIA Registers
Port Offset
Address
Name
Description
Page
Number
0x0D
UTOP1
UTOPIA Control Register 1
0x0E
UTOP2
UTOPIA Control Register 2
Table 7-8. Status and Interrupt Registers
Port Offset
Address
Name
Description
Page
Number
0x204
SUMPORT
Summary Port Interrupt Status Register
0x205
ENSUMPORT
Summary Port Interrupt Control Register
0x00
SUMINT
Summary Interrupt Indication Status Register
0x01
ENSUMINT
Summary Interrupt Control Register
0x28
ENCELLT
Transmit Cell Interrupt Control Register
0x29
ENCELLR
Receive Cell Interrupt Control Register)
0x2C
TXCELLINT
Transmit Cell Interrupt Indication Status Register
0x2D
RXCELLINT
Receive Cell Interrupt Indication Status Register
0x2E
TXCELL
Transmit Cell Status Register
0x2F
RXCELL
Receive Cell Status Register
Table 7-9. Counters (1 of 2)
Port Offset
Address
Name
Description
Page
Number
0x30
LOCDCNT
LOCD Event Counter
0x31
CORRCNT
Corrected HEC Error Counter
0x32
UNCCNT
Uncorrected HEC Error Counter
0x34
TXCNTL
Transmitted Cell Counter [Low Byte])
0x35
TXCNTM
Transmitted Cell Counter [Mid Byte]
0x36
TXCNTH
Transmitted Cell Counter [High Byte]
0x38
RXCNTL
Received Cell Counter [Low Byte]