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| 型号： | 33888A |
| 厂商： | Motorola, Inc. |
| 英文描述： | Quad High-Side and Octal Low-Side Switch for Automotive |
| 中文描述： | 四高边和八路低端汽车开关 |
| 文件页数： | 19/32页 |
| 文件大小： | 667K |
| 代理商： | 33888A |
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MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33888
19
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
This 33888 is a single-package combination of a power die
with four discrete high-side MOSFETs and an integrated IC
control die consisting of eight low-side drivers with appropriate
control, protection, and diagnostic features. The high-side
drivers are useful for both internal and external vehicle lighting
applications as well as capable of driving inductive solenoid
loads. The low-side drivers are capable of controlling low-
current on/off type inductive loads, such as relays and
solenoids as well as LED indicators and small lamps (see
simplified application diagram,
page 2
). The device is useful in
body control, instrumentation, and other high-power switching
applications and systems.
The 33888 is available in two packages: a power-enhanced
12 x 12 nonleaded Power QFN package with exposed tabs and
a 64-lead Power QFP plastic package.
Both packages are
intended to be soldered directly onto the printed circuit board.
The 33888 differs from the 33888A as explained in
Table 1
,
page 2.
FUNCTIONAL DESCRIPTION
SPI Interface and Protocol Description
The SPI interface has full duplex, three-wire synchronous
data transfer and has four I/O lines associated with it: Serial
Clock (SCLK), Serial Input (SI), Serial Output (SO), and Chip
Select (
CS
).
The SI/SO terminals of the 33888 follow a first-in first-out
(D15/D0) protocol with both input and output words transferring
the most significant bit first. All inputs are compatible with 5.0 V
CMOS logic levels. During SPI output control, a logic [0] in a
message word will result in the designated output being turned
off. Similarly, a logic [1] will turn on a corresponding output.
The SPI lines perform the following functions:
Serial Clock (SCLK)
The SCLK terminal clocks the internal shift registers of the
33888. The serial input (SI) terminal accepts data into the input
shift register on the falling edge of the SCLK signal while the
serial output terminal (SO) shifts data information out of the SO
line driver on the rising edge of the SCLK signal. It is important
that the SCLK terminal be in a logic [0] state whenever the chip
select (
CS
) makes any transition. For this reason, it is
recommended that the SCLK terminal be kept in a logic [0] state
as long as the device is not accessed (
CS
in logic [1] state).
SCLK has an active
internal pulldown, I
DWN
. When
CS
is
logic [1], signals at the SCLK and SI terminals are ignored and
SO is tri-stated (high impedance). (See
Figures 4
and
5
on
page 20
.)
Serial Interface (SI)
This is a serial interface (SI) command data input terminal.
Each SI bit is read on the falling edge of SCLK. A 16-bit stream
of serial data is required on the SI terminal, starting with D15 to
D0. The 12 outputs of the 33888 are configured and controlled
using the 3-bit addressing scheme and the 12 assigned data
bits designed into the 33888. SI has an active
internal pulldown,
I
DWN
.
Serial Output (SO)
The SO data terminal is a tri-stateable output from the shift
register. The SO terminal remains in a high-impedance state
until the
CS
terminal is put into a logic [0] state. The SO data
report the status of the outputs as well as provide the capability
to reflect the state of the direct inputs. The SO terminal changes
states on the rising edge of SCLK and reads out on the falling
edge of SCLK. When an output is ON or OFF and not faulted,
the corresponding SO bit, OD11:OD0, is a logic [0]. If the output
is faulted, the corresponding SO state is a logic [1]. SO
OD14:OD12 reflect the state of six various inputs (three at a
time) depending upon the reported state of the previously
written watchdog bit OD15.
Chip Select (
CS
)
The
CS
terminal enables communication with the master
microcontroller (MCU). When this terminal is in a logic [0] state,
the 33888 is capable of transferring information to and receiving
information from the MCU. The 33888 latches in data from the
input shift registers to the addressed registers on the rising
edge of
CS
. The 33888 transfers status information from the
power outputs to the shift registers on the falling edge of
CS
.
The output driver on the SO terminal is enabled when
CS
is
logic [0].
CS
is only transitioned from a logic [1] state to a
logic [0] state when SCLK is a logic [0].
CS
has an active
internal pullup, I
UP
.
The 33888 is capable of communicating directly with the
MCU via the 16-bit SPI protocol as described in the next
section.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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