参数资料
| 型号： | 34LC02T-I/SN |
| 厂商： | Microchip Technology |
| 文件页数： | 6/36页 |
| 文件大小： | 0K |
| 描述： | IC EEPROM 2KBIT 1MHZ 8SOIC |
| 产品培训模块： | I2C Serial EEPROM |
| 标准包装： | 3,300 |
| 格式 - 存储器： | EEPROMs - 串行 |
| 存储器类型： | EEPROM |
| 存储容量： | 2K (256 x 8) |
| 速度： | 1MHz |
| 接口： | I²C，2 线串口 |
| 电源电压： | 2.2 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 封装/外壳： | 8-SOIC（0.154"，3.90mm 宽） |
| 供应商设备封装： | 8-SOICN |
| 包装： | 带卷 (TR) |
| 其它名称： | 34LC02T-I/SNTR |
第1页第2页第3页第4页第5页当前第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页第32页第33页第34页第35页第36页
34AA02/34LC02
2.0
FUNCTIONAL DESCRIPTION
Each data transfer is initiated with a Start condition and
terminated with a Stop condition. The number of data
The 34XX02 has two Software Write-Protect features
that allow you to protect half of the array from being
written (Addresses 00h-7Fh). One command, Software
Write-Protect (SWP) will prevent writes to half of the
array and is resettable by using the Clear Software
Write-Protect (CSWP) command. The other command
is Permanent Software Write-Protect (PSWP), which is
bytes transferred between the Start and Stop
conditions is determined by the master device and is,
theoretically, unlimited; although only the last sixteen
will be stored when doing a write operation. When an
overwrite does occur, it will replace data in a first-in,
first-out (FIFO) fashion.
not resettable and will permanently lock half the array
3.5
Acknowledge
from being written to. The device still has an external
pin (WP) that allows you to protect the entire array if so
desired.
The 34XX02 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter, and a device
receiving data, as a receiver. The bus has to be
Each receiving device, when addressed, is obliged to
generate an Acknowledge after the reception of each
byte. Exceptions to this rule relating to software write
protection are described in Section 7.0 “Write Protec-
tion” . The master device must generate an extra clock
pulse, which is associated with this Acknowledge bit.
controlled by a master device, which generates the
Note:
The 34XX02 does not generate any
Serial Clock (SCL), controls the bus access and gener-
ates the Start and Stop conditions, while the 34XX02
works as slave. Both master and slave can operate as
transmitter or receiver, but the master device
determines which mode is activated.
Acknowledge bits if an internal
programming cycle is in progress.
The device that acknowledges has to pull down the
SDA line during the Acknowledge clock pulse in such a
way that the SDA line is stable low during the high
period of the acknowledge related clock pulse. Of
3.0
BUS CHARACTERISTICS
course, setup and hold times must be taken into
The following bus protocol has been defined:
? Data transfer may be initiated only when the bus
is not busy.
? During data transfer, the data line must remain
stable whenever the clock line is high. Changes in
the data line while the clock line is high will be
interpreted as a Start or Stop condition.
Accordingly, the following bus conditions have been
defined ( Figure 3-1 ).
account. During reads, a master must signal an end-of-
data to the slave by not generating an Acknowledge bit
on the last byte that has been clocked out of the slave.
In this case, the slave (34XX02) will leave the data line
high to enable the master to generate the Stop
condition.
3.1
Bus Not Busy (A)
Both data and clock lines remain high.
3.2
Start Data Transfer (B)
A high-to-low transition of the SDA line while the clock
(SCL) is high determines a Start condition. All
commands must be preceded by a Start condition.
3.3
Stop Data Transfer (C)
A low-to-high transition of the SDA line while the clock
(SCL) is high determines a Stop condition. All
operations must be ended with a Stop condition.
3.4
Data Valid (D)
The state of the data line represents valid data when,
after a Start condition, the data line is stable for the
duration of the high period of the clock signal.
The data on the line must be changed during the low
period of the clock signal. There is one clock pulse per
bit of data.
DS22029F-page 6
? 2011 Microchip Technology Inc.
相关PDF资料 |
PDF描述 |
|---|---|
| RMC65DRTH-S13 | CONN EDGECARD 130PS .100 EXTEND |
| 24AA02HT-I/SN | IC EEPROM 2KBIT 400KHZ 8SOIC |
| 93AA56AT-I/OT | IC EEPROM 2KBIT 2MHZ SOT23-6 |
| AMC30DRYS | CONN EDGECARD 60POS .100 DIP SLD |
| AMM24DTKT-S288 | CONN EDGECARD 48POS .156 EXTEND |
相关代理商/技术参数 |
参数描述 |
|---|---|
| 34LLW | 制造商:Thomas & Betts 功能描述:ADVANTAGES OF STEEL CITY COMMERCIAL CONDUIT FITTINGS |
| 34M4084 | 制造商:Distributed By MCM 功能描述:470 UF 450 VDC 500 SURGE CAPACITOR 82 DA SERIES |
| 34MCX-50-0-2 | 制造商:HUBER+SUHNER 功能描述:IN SERIES ADAPTER |
| 34MCX-N-50-1/3E | 制造商:HUBER+SUHNER 功能描述:BETWEEN SERIES ADAPTER |
| 34MMCX-50-0-1/1 | 制造商:HUBER+SUHNER 功能描述:IN SERIES ADAPTER |
发布紧急采购，3分钟左右您将得到回复。