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参数资料
| 型号： | 4022-DKDB13 |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 14/20页 |
| 文件大小： | 726K |
| 描述： | KIT DEV TEST EZRADIO SI4022 TX |
| 标准包装： | 1 |
| 附件类型： | 测试卡，发射器，868MHz，915MHz |
| 适用于相关产品： | EZRadio? |
14
Si4022
bw1 bw0
PLL bandwidth
0
0
15 kHz
0
1
30 kHz
1
0
60 kHz
1
1
120 kHz
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
POR
1
0
1
1
0
0
0
0 exlp ctls 0 dcal bw1 bw0 dsfi ewi
B0CAh
FFIT
The number of data bits in the FIFO has gone below the preprogrammed limit
FFEM
FIFO is empty
FFOV
FIFO overflow
LBD
Low battery detect, the power supply voltage is below the preprogrammed limit
WK-UP
Wake-up timer overflow
POR
Power-on reset
bit 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
POR
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-
Status Register Read Command
With this command, it is possible to read the status register of the chip through the SDO pin.
Status Register Read Sequence
Extended Features Command:
Bit 7 <exlp>:
Enables low power mode for the crystal oscillator.
Bit 6 <ctls>:
Clock tail selection bit. Setting this bit selects 512 cycle long clock tail instead of the default 128.
Bit 4 <dcal>:
Disables the wake-up timer autocalibration.
Bit 3-2 <bw1:bw0>: Select the bandwidth of the PLL.
Bit 1 <dsfi>:
Disables autosleep on FIFO interrupt if set to 1.
Bit 0 <ewi>:
Enables the automatic wake-up on any interrupt event.
nSEL
SCK
SDI
SDO
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
status out
FFIT
FFEM
FFOV
LBD
WK-UP
POR
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