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| 型号： | 4022-DKDB13 |
| 厂商： | Silicon Laboratories Inc |
| 文件页数： | 15/20页 |
| 文件大小： | 726K |
| 描述： | KIT DEV TEST EZRADIO SI4022 TX |
| 标准包装： | 1 |
| 附件类型： | 测试卡，发射器，868MHz，915MHz |
| 适用于相关产品： | EZRadio? |
15
Si4022
Dual Clock Output
When the chip is switched into idle mode, the 10 MHz crystal oscillator starts. After oscillation ramp-up a 1 MHz clock signal is
available on the CLK pin. This (fast) clock frequency can be reprogrammed during operation with the Low Battery and Microcontroller
Clock Divider Command (page13). During startup and in sleep or standby mode (crystal oscillator disabled), the CLK output is pulled
to logic low.
On the same pin a low frequency clock signal can be obtained if the elfc bit is set in the Low Battery and Microcontroller Clock Divider
Command. The clock frequency is 32 kHz which is derived from the low-power RC oscillator of the wake-up timer. In order to use this
slow clock the wake-up timer should be enabled by setting the et bit in the Power Management Command (page 11) even if the wake-
up timer itself is not used.
Slow clock feature can be enabled by entering into sleep mode (page 11). Driving the output will increase the sleep mode supply
current. Actual worst-case value can be determined when the exact load and min/max operating conditions are defined. After power-
on reset the chip goes into sleep mode and the slow frequency clock appears on the CLK pin.
Switching back into fast clock mode can be done by setting the ex or etr bits in the approriate commands. It is important to leave bit
dc in the Power Management Command at its default state (0) otherwise there will be no clock signal on the CLK pin.
Switching between the fast and slow clock modes is glitch-free in a sense that either state of the clock lasts for at least a half cycle
of the fast clock. During switching the clock can be logic low once for an intermediate period i.e. for any time between the half cycle
of the fast and the slow clock.
The clock switching synchronization circuit detects the falling edges of the clocks. One consequence is a latency of 0 to T
slow
+ T
fast
from the
occurrence of a clock change request (entering into sleep mode or interrupt) until the beginning of the intermediate length (T
x
) half cycle. The
other is that both clocks should be up and running for the change to occur. Changing from fast to slow clock, it is automatically ensured by
entering into the sleep mode in the appropriate way provided that the wake-up timer is continouosly enabled. As the crystal oscillator is
normally stopped while the slow clock is used, when changing back to fast clock the crystal oscillator startup time has to pass first before the
above mentioned latency period starts. The startup condition is detected internally, so no software timing is necessary.
Wake-Up Timer Calibration
By default the wake-up timer is calibrated each time it is enabled by setting the et bit in the Power Management Command. After
timeout the timer can be stopped by resetting this bit otherwise it operates continuously. If the timer is programmed to run for longer
periods, at approximately every 40 seconds it performs additional self-calibration.
This feature can be disabled to avoid sudden changes in the actual wake-up time period. A suitable software algorithm can then
compensate for the gradual shift caused by temperature change.
Bit dcal in the Extended Features Command (page 14) controls the automatic calibration feature. It is reset to 0 at power-on and the
automatic calibration is enabled. This is necessary to compensate for process tolerances. After one calibration cycle further
(re)calibration can be disabled by setting this bit to 1.
fast clock
clock periods are not to scale
T
slow
output
slow clock
T
fast
T
x
0.5 * T
fast
< T
x
< 0.5 * T
slow
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