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| 型号： | 4306-52 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC DSA 5BIT 50 OHM 20-QFN |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 衰减值： | 31dB |
| 容差： | ±0.3dB |
| 频率范围： | 0 ~ 4GHz |
| 阻抗： | 50 欧姆 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 其它名称： | 1046-1033-6 |
PE4306
Product Specification
Evaluation Kit
The Digital Attenuator Evaluation Kit board was
designed to ease customer evaluation of the
PE4306 DSA.
J9 is used in conjunction with the supplied DC
cable to supply V DD , GND, and –V DD . If use of the
internal negative voltage generator is desired,
then connect –V DD (black banana plug) to ground.
If an external –V DD is desired, then apply -3V.
J1 should be connected to the LPT1 port of a PC
with the supplied control cable. The evaluation
software is written to operate the DSA in serial
mode, so switch 7 (P/S) on the DIP switch SW1
should be ON with all other switches off. Using the
software, enable or disable each attenuation
setting to the desired combined attenuation. The
software automatically programs the DSA each
time an attenuation state is enabled or disabled.
To evaluate the power up options, first disconnect
the control cable from the evaluation board. The
control cable must be removed to prevent the PC
port from biasing the control pins.
During power up with P/S = 1 high and LE = 0 or
P/S = 0 low and LE = 1, the default power-up
signal attenuation is set to the value present on
the five control bits on the five parallel data inputs
(C1 to C16). This allows any one of the 32
attenuation settings to be specified as the power-
up state.
During power up with P/S = 0 high and LE = 0, the
control bits are automatically set to one of four
possible values presented through the PUP
interface. These four values are selected by the
two power-up control bits, PUP1 and PUP2, as
shown in the Table 6 .
Pin 20 is open and can be connected to any bias.
Resistor on Pin 1 & 3
A 10 k ? resistor on the inputs to pins 1 & 3
(Figure 16) will eliminate package resonance
between the RF input pin and the two digital
inputs. Specified attenuation error versus
frequency performance is dependent upon this
condition.
Document No. DOC-30007-2 │ www.psemi.com
Figure 15. Evaluation Board Layout
DOC-02344
?2003-2013 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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