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| 型号： | 4308-52 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 2/11页 |
| 文件大小： | 0K |
| 描述： | IC DSA 5BIT 75 OHM 20-QFN |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 衰减值： | 31dB |
| 容差： | ±0.2dB |
| 频率范围： | 0 ~ 2GHz |
| 阻抗： | 75 欧姆 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 其它名称： | 1046-1035-6 |
PE4308
Product Specification
Figure 14. Pin Configuration (Top View)
Table 3. Absolute Maximum Ratings
Symbol
V DD
V I
Parameter/Conditions
Power supply voltage
Voltage on any input
Min
-0.3
-0.3
Max
4.0
V DD +
0.3
Units
V
V
C16
RF1
Data
Clock
1
2
3
4
20-lead
QFN
4x4mm
Exposed Solder Pad
15
14
13
12
C8
RF2
P/S
Vss/GND
T ST
P IN
V ESD
Storage temperature range
Input power (50 ? )
ESD voltage (Human Body
Model)
-65
150
+30
500
°C
dBm
V
LE
5
11
GND
Table 4. Operating Ranges
Parameter
V DD Power Supply
Voltage
Min
2.7
Typ
3.0
Max
3.3
Units
V
Table 2. Pin Descriptions
I DD Power Supply
Current
Digital Input High
0.7xV DD
100
μ A
V
Pin
No.
1
2
Pin
Name
C16
RF1
Description
Attenuation control bit, 16dB (Note 4).
RF port (Note 1).
Digital Input Low
Digital Input Leakage
Input Power
0.3xV DD
1
+24
V
μ A
dBm
3
4
Data
Clock
Serial interface data input (Note 4).
Serial interface clock input.
Temperature range
-40
85
°C
5
LE
Latch Enable input (Note 2).
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Paddle
V DD
PUP1
PUP2
V DD
GND
GND
V ss /GND
P/S
RF2
C8
C4
C2
GND
C1
N/C
GND
Power supply pin.
Power-up selection bit.
Power-up selection bit.
Power supply pin.
Ground connection.
Ground connection.
Negative supply voltage or GND
connection (Note 3)
Parallel/Serial mode select.
RF port (Note 1).
Attenuation control bit, 8 dB.
Attenuation control bit, 4 dB.
Attenuation control bit, 2 dB.
Ground connection.
Attenuation control bit, 1 dB.
No connect
Ground for proper operation
Exposed Solder Pad Connection
The exposed solder pad on the bottom of the
package must be grounded for proper device
operation.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS? device, observe
the same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rate specified in Table 3.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS?
devices are immune to latch-up.
Switching Frequency
Notes: 1: Both RF ports must be held at 0 V DC or DC blocked with an
external series capacitor.
2: Latch Enable (LE) has an internal 100 k ? resistor to V DD.
3: Connect pin 12 to GND to enable internal negative voltage
generator. Connect pin 12 to V SS (-V DD ) to bypass and
disable internal negative voltage generator.
4. Place a 10 k ? resistor in series, as close to pin as possible
to avoid frequency resonance. See “Resistor on Pin 1 & 3”
paragraph
?2003-2006 Peregrine Semiconductor Corp. All rights reserved.
The PE4308 has a maximum 25 kHz switching rate.
Resistor on Pin 1 & 3
A 10 k ? resistor on the inputs to Pin 1 & 3 (see
Figure 5) will eliminate package resonance between
the RF input pin and the two digital inputs. Specified
attenuation error versus frequency performance is
dependent upon this condition.
Document No. 70-0162-04 │ UltraCMOS? RFIC Solutions
Page 2 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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