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参数资料
| 型号： | 4308-52 |
| 厂商： | Peregrine Semiconductor |
| 文件页数： | 7/11页 |
| 文件大小： | 0K |
| 描述： | IC DSA 5BIT 75 OHM 20-QFN |
| 标准包装： | 1 |
| 系列： | UltraCMOS™ |
| 衰减值： | 31dB |
| 容差： | ±0.2dB |
| 频率范围： | 0 ~ 2GHz |
| 阻抗： | 75 欧姆 |
| 封装/外壳： | 20-WFQFN 裸露焊盘 |
| 其它名称： | 1046-1035-6 |
PE4308
Product Specification
Programming Options
Parallel/Serial Selection
Either a parallel or serial interface can be used to
control the PE4308. The P/S bit provides this
selection, with P/S=LOW selecting the parallel
interface and P/S=HIGH selecting the serial
interface.
Parallel Mode Interface
The parallel interface consists of five CMOS-
compatible control lines that select the desired
attenuation state, as shown in Table 5.
The parallel interface timing requirements are
defined by Figure 19 (Parallel Interface Timing
Diagram), Table 9 (Parallel Interface AC
Characteristics), and switching speed (Table 1).
For latched parallel programming the Latch Enable
(LE) should be held LOW while changing attenuation
state control values, then pulse LE HIGH to LOW
(per Figure 19) to latch new attenuation state into
device.
For direct parallel programming, the Latch Enable
(LE) line should be pulled HIGH. Changing
attenuation state control values will change device
state to new attenuation. Direct Mode is ideal for
manual control of the device (using hardwire,
switches, or jumpers).
Table 5. Truth Table
serially entered into the shift register, a process that
is independent of the state of the LE input.
The LE input controls the latch. When LE is HIGH,
the latch is transparent and the contents of the serial
shift register control the attenuator. When LE is
brought LOW, data in the shift register is latched.
The shift register should be loaded while LE is held
LOW to prevent the attenuator value from changing
as data is entered. The LE input should then be
toggled HIGH and brought LOW again, latching the
new data. The stop bit (B0) of the data should
always be low to prevent an unknown state in the
device. The timing for this operation is defined by
Figure 17 (Serial Interface Timing Diagram) and
Table 8 (Serial Interface AC Characteristics).
Power-up Control Settings
The PE4308 always assumes a specifiable
attenuation setting on power-up. This feature exists
for both the Serial and Parallel modes of operation,
and allows a known attenuation state to be
established before an initial serial or parallel control
word is provided.
When the attenuator powers up in Serial mode (P/
S=1), the five control bits and a stop bit are set to
whatever data is present on the five parallel data
inputs (C1 to C16). This allows any one of the 32
attenuation settings to be specified as the power-up
state.
P/S
0
0
0
0
0
0
0
C16
0
0
0
0
0
1
1
C8
0
0
0
0
1
0
1
C4
0
0
0
1
0
0
1
C2
0
0
1
0
0
0
1
C1
0
1
0
0
0
0
1
Attenuation State
Reference Loss
1 dB
2 dB
4 dB
8 dB
16 dB
31 dB
When the attenuator powers up in Parallel mode (P/
S=0) with LE=0, the control bits are automatically set
to one of four possible values. These four values
are selected by the two power-up control bits, PUP1
and PUP2, as shown in Table 6 (Power-Up Truth
Table, Parallel Mode).
Table 6. Power-Up Truth Table, Parallel
Interface Mode
Note: Not all 32 possible combinations of C1-C16 are shown.
Serial Interface
The PE4308’s serial interface is a 6-bit serial-in,
parallel-out shift register buffered by a transparent
latch. The latch is controlled by three CMOS-
P/S
0
0
0
0
0
LE
0
0
0
0
1
PUP2
0
0
1
1
X
PUP1
0
1
0
1
X
Attenuation State
Reference Loss
8 dB
16 dB
31 dB
Defined by C1-C16
compatible signals: Data, Clock, and Latch Enable
Note:
Power up with LE=1 provides normal parallel operation
(LE). The Data and Clock inputs allow data to be
Document No. 70-0162-04 │ www.psemi.com
with C1-C16, and PUP1 and PUP2 are not active.
?2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 7 of 11
Logo updated under non-rev change. Peregrine products are protected under one or more of the following U.S. Patents: http://patents.psemi.com
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