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参数资料
| 型号： | 514NBBXXXXXXBAGR |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | 时钟产生/分配 |
| 英文描述： | 170 MHz, OTHER CLOCK GENERATOR, PDSO6 |
| 封装： | 3.20 X 5 MM, ROHS COMPLIANT PACKAGE-6 |
| 文件页数： | 7/32页 |
| 文件大小： | 267K |
| 代理商： | 514NBBXXXXXXBAGR |
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Si514
Preliminary Rev. 0.9
15
3. All-Digital PLL Applications
The Si514 uses a high resolution divider M that enables fine frequency adjustments with resolution better than
0.026 parts per billion. Fine frequency adjustments are useful when making frequency corrections that compensate
for changing ambient conditions, long term aging or when locking the Si514 to an input clock reference. Figure 3
shows a typical implementation using a system IC such as an FPGA to control the output of the Si514 in a phase-
locked application. Refer to “AN575: An Introduction to FPGA-Based ADPLLs” for more information.
Figure 3. All-Digital PLL Application Using Si514 with Dual CMOS Output
Since small frequency changes must be within ±1000 ppm of the center frequency, HS_DIV and LS_DIV remain
constant. The below expression can be used to calculate a new M2 divider value based on a desired output
frequency shift, where FOUT is in ppm.
Some systems, particularly those that use feedback control, can simplify the computation by implementing an
approximate frequency change based on toggling a bit position or adding/subtracting a bit to the existing M_Frac
value. Since M ranges approximately ±10% between 65.04065041 and 78.17385866, the effect of changing
M_Frac by a single bit depends only slightly on the absolute value of M.
For M=71 near the midpoint of the range, toggling M_Frac[0] changes the output frequency by 0.026 ppb. Each
higher order bit doubles the influence such that toggling M_Frac[1] is 0.052 ppb, M_Frac[2] is 0.1 ppb, etc. Figure 4
shows this trend across multiple registers generalized to M_Frac[N]. Coarse changes greater than ±1.7 ppm are
possible but most applications require finer transitions. Toggling each bit involves incrementing or decrementing
the bit position. Writing M_Int[8:3] in register 9 completes the operation.
Figure 4. Output Frequency Change When Toggling M_Frac[N], M=71
I2C Control
Any Frequency
DSPLL
CLK_OUT
FB
Si514
FPGA
÷
I2C
Master
Command
Conversion
Loop
Filter
PD
÷
SCL
SDA
Fin
M2
M1 1 FOUT 10
6
–
–
=
M_Int[8:0] = 000100111
M = 71.000000000000
M_Frac[28:0] = 00000000000000000000000000000
M_Frac[23:16] = 00000000
M_Frac[15:8] = 00000000
M_Frac[7:0] = 00000000
0.026ppb
6.7ppb
1.7ppm
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 514NCA000208AAG | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays |
| 514NCA000208AAGR | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Tape and Reel |
| 514NCA000688BAG | 功能描述:标准时钟振荡器 PROGRMABLE XO 6 PIN 0.7PS RS JTR RoHS:否 制造商:AVX 产品:Standard Clock Oscillators 封装 / 箱体:7 mm x 5 mm 频率:75 MHz 频率稳定性:50 PPM 电源电压:2.5 V 负载电容: 端接类型:SMD/SMT 最小工作温度:0 C 最大工作温度:+ 70 C 输出格式:LVDS 尺寸: 封装:Reel 系列: |
| 514NCA000688BAGR | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Tape and Reel |
| 514NCA000776AAG | 制造商:Silicon Laboratories Inc 功能描述:OSCILLATOR - Trays |
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