参数资料
型号: 554AD000159DGR
厂商: SILICON LABORATORIES
元件分类: VCXO, clock
英文描述: VCXO, CLOCK, LVPECL OUTPUT
封装: ROHS COMPLIANT PACKAGE-8
文件页数: 13/14页
文件大小: 238K
代理商: 554AD000159DGR
Si554
8
Rev. 0.6
3. Ordering Information
The Si554 supports a variety of options including frequency, temperature stability, tuning slope, output format, and
VDD.
Specific device configurations are programmed into the Si554 at time of shipment. Configurations are
specified using the Part Number Configuration chart shown below. Silicon Labs provides a web browser-based part
number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this tool
and for further ordering instructions. The Si554 VCXO series is supplied in an industry-standard, RoHS-compliant,
lead-free, 8-pad, 5 x 7 mm package. Tape and reel packaging is an ordering option.
Figure 1. Part Number Convention
Example Part Number: 554AF000124DGR is a 5 x 7 mm Quad VCXO in an 8 pad package. Since the six digit code (000124) is > 000100, f0 is
622.08 MHz (lowest frequency), f1 is 644.53125, f2 is 657.42188, and f3 is 669.32658 MHz (highest frequency), with a 3.3 V supply, LVPECL
output, and Output Enable active high polarity. Temperature stability is specified as ±50 ppm and the tuning slope is 135 ppm/V. The part is specified
for a –40 to +85 C° ambient temperature range operation and is shipped in tape and reel format.
R = Tape & Reel
Blank = Trays
Operating Temp Range (°C)
G–40 to +85 °C
Device Revision Letter
554 Quad VCXO
Product Family
6-digit Frequency Designator Code
Four unique frequencies can be specified within the following bands of frequencies: 10 to
945 MHz, 970 to 1134 MHz, and 1213 to 1417 MHz. A six digit code will be assigned for
the specified combination of frequencies. Codes > 000100 refer to XOs programmed with
the lowest frequency value selected when FS[1:0] = 00, and the highest value when
FS[1:0] = 11. Six digit codes < 000100 refer to XOs programmed with the highest
frequency value selected when FS[1:0] = 00, and the lowest value when FS[1:0] = 11.
554
X
XXXXXX
D
G
R
1st Option Code
VDD
Output Format Output Enable Polarity
A
3.3
LVPECL
High
B
3.3
LVDS
High
C
3.3
CMOS
High
D3.3
CML
High
E
2.5
LVPECL
High
F
2.5
LVDS
High
G
2.5
CMOS
High
H2.5
CML
High
J
1.8
CMOS
High
K1.8
CML
High
M
3.3
LVPECL
Low
N
3.3
LVDS
Low
P3.3
CMOS
Low
Q3.3
CML
Low
R
2.5
LVPECL
Low
S
2.5
LVDS
Low
T2.5
CMOS
Low
U2.5
CML
Low
V1.8
CMOS
Low
W1.8
CML
Low
Note:
CMOS available to 160 MHz.
2nd Option Code
Temperature
Tuning Slope
Minimum APR
Stability
Kv
(±ppm) for VDD @
Code
± ppm (max)
ppm/V (typ)
3.3 V
2.5 V
1.8 V
A
100
180
100
75
25
B
100
90
30
Note 6
C
50
180
150
125
75
D
509080
30
25
E
204525
Note 6
F50
135
100
75
50
G
20
356
375
300
235
H
20
180
185
145
105
J
20
135
130
104
70
K
100
356
295
220
155
M
20
33
12
Note 6
Notes:
1. For best jitter and phase noise performance, always choose the smallest Kv that meets
the application’s minimum APR requirements. Unlike SAW-based solutions which
require higher higher Kv values to account for their higher temperature dependence,
the Si55x series provides lower Kv options to minimize noise coupling and jitter in real-
world PLL designs. See AN255 and AN266 for more information.
2. APR is the ability of a VCXO to track a signal over the product lifetime. A VCXO with an
APR of ±25 ppm is able to lock to a clock with a ±25 ppm stability over 15 years over all
operating conditions.
3. Nominal Pull range (±) = 0.5 x VDD x tuning slope.
4. Nominal Absolute Pull Range (±APR) = Pull range – stability – lifetime aging
= 0.5 x VDD x tuning slope – stability – 10 ppm
5. Minimum APR values noted above include worst case values for all parameters.
6. Combination not available.
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