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参数资料
型号： 570FBC000136DG
厂商： SILICON LABORATORIES
元件分类： XO, clock
英文描述： CRYSTAL OSCILLATOR, CLOCK, 10 MHz - 280 MHz, LVDS OUTPUT
封装： ROHS COMPLIANT PACKAGE-8
文件页数： 21/30页
文件大小： 361K
代理商： 570FBC000136DG
Si570/Si571
28
Rev. 1.1
DOCUMENT CHANGE LIST
Revision 0.1 to Revision 0.2
Updated " Description" on page 1.
Updated "1. Detailed Block Diagrams" on page 4 for
both XO and VCXO.
Updated the Nominal Control Voltage in Table 2, “VC
Control Voltage Input,” on page 5.
Updated tables to reflect slight performance
differences between Si570 and Si571.
Added detail to the "3.2. I2C Interface" on page 16.
Revised "3.2.3. Programming Procedure" on page
12.
Procedure now requires use of two frequency
configuration register sets.
Procedure now recommends disabling output at
powerup to protect equipment not expecting the
default output frequency.
Added second frequency configuration register set
to the register tables.
Added frequency configuration select register.
Updated "7. Ordering Information" on page 24 to be
consistent with the Si55x series devices.
Revision 0.2 to Revision 0.3
Updated Table 1, “Recommended Operating
Conditions,” on page 5.
Device maintains stable operation over –40 to +85 C
operating temperature range.
Supply current specifications updated.
Updated Table 4, “CLK± Output Levels and
Symmetry,” on page 7.
Updated LVDS differential peak-peak swing
specifications.
Updated Table 5, “CLK± Output Phase Jitter
(Si570),” on page 7.
Updated Table 6, “CLK± Output Phase Jitter
(Si571),” on page 8.
Updated Table 7, “CLK± Output Period Jitter,” on
page 10.
Revised period jitter specifications.
Updated Table 10, “Absolute Maximum Ratings,” on
page 11 to reflect the soldering temperature time at
260 C is 20–40 sec per JEDEC J-STD-020C.
Updated device programming procedure in Section
"3.2.3. Programming Procedure" on page 12.
Updated "7. Ordering Information" on page 24.
Changed ordering instructions to revision D.
Added "8. Si57x Mark Specification" on page 25.
Revision 0.3 to Revision 0.31
Updated "3.2.3. Programming Procedure" on page
12.
Corrected Step 6 to read “bit 4”.
Corrected Freeze DCO bit location in Register 137 to
bit 4 on pages 14 and 18.
Revision 0.31 to Revision 1.0
Updated " Functional Block Diagram" on page 1.
Updated Figure 1, “Si570 Detailed Block Diagram,”
on page 4.
Updated Figure 2, “Si571 Detailed Block Diagram,”
on page 4.
Updated Figure 6, “Part Number Convention,” on
page 24.
Updated Table 1, “Recommended Operating
Conditions,” on page 5.
Updated Table 3, “CLK± Output Frequency
Characteristics,” on page 6.
Updated Table 6, “CLK± Output Phase Jitter
(Si571),” on page 8.
Updated Table 12, “Programming Constraints and
Timing,” on page 12.
Updated Table 12, “Programming Constraints and
Timing,” on page 12.
Updated "3. Functional Description" on page 13.
Updated "3.1. Programming a New Output
Frequency" on page 13.
Updated "3.1.1. Reconfiguring the Output Clock for a
Small Change in Frequency" on page 13.
Updated "3.1.2. Reconfiguring the Output Clock for
Large Changes in Output Frequency" on page 14.
Updated “7.Ordering Information”.
Updated Figure 6, “Part Number Convention,” on page
24.
Revision 1.0 to Revision 1.1
Restored programming constraint information on
page 15 and in Table 12, page 12.
Clarified NC (No Connect) pin designations in Tables
13–14 on pages 22–23.
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