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| 型号： | 570FBC000136DG |
| 厂商： | SILICON LABORATORIES |
| 元件分类： | XO, clock |
| 英文描述： | CRYSTAL OSCILLATOR, CLOCK, 10 MHz - 280 MHz, LVDS OUTPUT |
| 封装： | ROHS COMPLIANT PACKAGE-8 |
| 文件页数： | 8/30页 |
| 文件大小： | 361K |
| 代理商： | 570FBC000136DG |
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Si570/Si571
16
Rev. 1.1
3.2. I2C Interface
The control interface to the Si570 is an I2C-compatible
2-wire bus for bidirectional communication. The bus
consists of a bidirectional serial data line (SDA) and a
serial clock input (SCL). Both lines must be connected
to the positive supply via an external pullup.Fast mode
operation is supported for transfer rates up to 400 kbps
as specified in the I2C-Bus Specification standard.
Figure 5 shows the command format for both read and
write access. Data is always sent MSB. Data length is 1
byte. Read and write commands support 1 or more data
bytes as illustrated. The master must send a Not
Acknowledge and a Stop after the last read data byte to
terminate the read command. The timing specifications
and timing diagram for the I2C bus can be found in the
I2C-Bus Specification standard (fast mode operation).
The device I2C address is specified in the part number.
Figure 5. I2C Command Format
From master to slave
From slave to master
A – Acknowledge (SDA LOW)
N – Not Acknowledge (SDA HIGH).
Required after the last data byte to signal the end of the read comand to the slave.
S – START condition
P – STOP condition
P
A
Byte Address
A
S Slave Address 0
Data
Write Command
(Optional 2nd data byte and acknowledge illustrated)
A
Byte Address
A
S Slave Address 0
S Slave Address 1
A
Data
A
Data
N P
Read Command
(Optional data byte and acknowledge before the last data byte and not acknowledge illustrated)
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