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| 型号： | 5962-9169201QXC |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | ADC |
| 英文描述： | 2-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP28 |
| 封装： | CERAMIC, DIP-28 |
| 文件页数： | 18/39页 |
| 文件大小： | 334K |
| 代理商： | 5962-9169201QXC |
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MAX6954
4-Wire Interfaced, 2.7V to 5.5V LED Display
Driver with I/O Expander and Key Scan
______________________________________________________________________________________
25
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Configuration
Register
PI
R
T
E
B
X
S
Table 16. Configuration Register Format
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Shutdown
PI
R
T
E
B
X
0
Normal
Operation
PI
R
T
E
B
X
1
Table 17. Shutdown Control (S Data Bit DO)
Format
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Slow blinking. Segments blink on for 1s, off for 1s with fOSC = 4MHz.
P
I
RT
E
0
X
S
Fast blinking. Segments blink on for 0.5s, off for 0.5s with fOSC = 4MHz.
P
I
RT
E
1
X
S
Table 18. Blink Rate Selection (B Data Bit D2) Format
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Blink function is disabled.
P
I
R
T
0
B
X
S
Blink function is enabled.
P
I
R
T
1
B
X
S
Table 19. Global Blink Enable/Disable (E Data Bit D3) Format
SEGMENT’S BIT SETTING
IN PLANE P1
SEGMENT’S BIT SETTING
IN PLANE P0
SEGMENT
BEHAVIOR
0
Segment off.
01
Segment on only during the 1st half of each
blink period.
10
Segment on only during the 2nd half of each
blink period.
1
Segment on.
Table 20. Digit Register Mapping with Blink Globally Enabled
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Blink timing counters are unaffected.
P
I
R
0
E
B
X
S
Blink timing counters are reset on the rising edge of
CS.P
I
R
1
E
B
X
S
Table 21. Global Blink Timing Synchronization (T Data Bit D4) Format
REGISTER DATA
MODE
D7
D6
D5
D4
D3
D2
D1
D0
Digit data for both planes P0 and P1 are unaffected.
P
I
0T
E
B
X
S
Digit data for both planes P0 and P1 are cleared on the rising edge of
CS.
P
I
1T
E
B
X
S
Table 22. Global Clear Digit Data (R Data Bit D5) Format
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