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参数资料
| 型号： | 5962-9751801MPA |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | 运算放大器 |
| 英文描述： | OP-AMP, CDIP8 |
| 封装： | DIP-8 |
| 文件页数： | 5/8页 |
| 文件大小： | 316K |
| 代理商： | 5962-9751801MPA |
Figure 1 shows the noise model for the non-inverting
amplifier configuration. The model includes all of the
following noise sources:
Input voltage noise (en)
Input current noise (in = in+ = in-)
Thermal Voltage Noise (et) associated with each
external resistor
Figure 1: Non-inverting Amplifier Noise Model
The total equivalent input noise density is calculated
by using the noise model shown. Equations 1 and 2
represent the noise equation and the resulting equation
for noise figure.
Equation 1: Noise Equation
Equation 2: Noise Figure Equation
The noise figure is related to the equivalent source
resistance (Rseq) and the parallel combination of Rf and
Rg. To minimize noise figure, the following steps are
recommended:
Minimize RfIIRg
Choose the optimum Rs (ROPT)
ROPT is the point at which the NF curve reaches a
minimum and is approximated by:
Figure 2 is a plot of NF vs Rs with Rf = 0, Rg = ∞ (Av = +1).
The NF curves for both Unterminated and Terminated
systems are shown. The Terminated curve assumes Rs
= RT. The table indicates the NF for various source resis-
tances including Rs = ROPT.
Layout Considerations
A proper printed circuit layout is essential for achieving
high
frequency
performance.
National
provides
evaluation boards for the CLC440 (CLC730055-DIP,
CLC730060-SOIC) and suggests their use as a guide for
high frequency layout and as an aid in device testing and
characterization.
Figure 2: Noise Figure vs. Source Resistance
These boards were laid out for optimum, high-speed
performance. The ground plane was removed near the
input and output pins to reduce parasitic capacitance.
And all trace lengths were minimized to reduce series
inductances.
Supply
bypassing
is
required
for
the
amplifiers
performance.
The bypass capacitors provide a low
impedance return current path at the supply pins. They
also provide high frequency filtering on the power supply
traces. 6.8
F tantalum, 0.01F ceramic, and 500pF
ceramic capacitors are recommended on both supplies.
Place the 6.8
F capacitors within 0.75 inches of the
power pins, and the 0.01
F and 500pF capacitors less
than 0.1 inches from the power pins.
Dip sockets add parasitic capacitance and inductance
which can cause peaking in the frequency response and
overshoot in the time domain response. If sockets are
necessary, flush-mount socket pins are recommended.
The device holes in the 730055 evaluation board are
sized for Cambion P/N 450-2598 socket pins, or their
functional equivalent.
Transimpedance Amplifier
The low 2.5pA/
√Hz input current noise and unity gain
stability make the CLC440 an excellent choice for
transimpedance applications.
Figure 3 illustrates a
low noise transimpedance amplifier that is commonly
implemented with photo diodes. Rf sets the transimped-
ance gain. The photo diode current multiplied by Rf
determines the output voltage.
Figure 3: Transimpedance Amplifier Configuration
Rseq
Rf
+
-
Rg
CLC440
*
in+
*
en
in-
*
4kTRseq
4kTR
f
4kTRg
Rseq = Rs for Unterminated Systems
Rseq = Rs II RT for Terminated Systems
Noise Figure vs. Source Resistance
Noise
Figure
(dB)
Source Resistance (
)
10
100k
Unterminated
Terminated
10
15
20
25
100
1k
10k
5
0
Ropt = 2800
Ropt = 1400
Rs()
50
ROPT
NF Unterminated
12.03dB
3.13dB
NF Terminated
17.90dB
6.15dB
Applications Circuits
Iin
-
+
CLC440
Cd
Rf
Cf
Photo Diode
Representation
Vout = -Iin*Rf
Vout
e
i
R
R IIR
4kTR
4kT R IIR
ni
n
2
n
2
seq
2
f
g
2
seq
f
g
=+
+
()
++
()
NF
10LOG
e
i
R
R IIR
4kTR
4kT R IIR
4kTR
n
2
n
2
seq
2
f
g
2
seq
f
g
seq
=
++
()
++
()
R
e
i
OPT
n
5
http://www.national.com
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