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参数资料
| 型号： | 5962-9855201QZX |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CQFP132 |
| 封装： | QFP-132 |
| 文件页数： | 14/64页 |
| 文件大小： | 1464K |
| 代理商： | 5962-9855201QZX |
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21
After the UT69R000 recognizes the current bus cycle is
finished, DS becomes inactive (transition from low to high) on
the first rising edge of OSCIN after the end of time period CK4.
The bus cycle completely ends one full clock cycle after the
end of time period CK4, when BGACK, R/WR, and the
Operand Address and Data buses enter a high-impedance state.
4.2 DMS Operation and Bus Arbitration
Figure 22 shows the timing diagram of the signal relationships
for the UT69R000 during a DMA operation. For DMA
operations, multipurprocessor, and Operand bus arbitration
functions, the UT69R000 provides four active-low control
signals for managing the Operand bus and preventing bus
contention. These signals are Bus Request (BRQ, Bus Grant
(BGNT), Bus Busy (BUSY), and Bus Grant Acknowledge
(BGACK).
Each of the four bus control signals provides a specific function
for controlling Operand bus operation. The function of each
of the four signals is given below.
Bus Request (BRQ)
The UT69R000 generates BRQ to indicate a request to use the
Operand buses. The UT69R000 retains control of the buses by
keeping the BGACK signal active until it no longer requires
the buses.
Bus Grant (BGNT)
An external arbitrator generates this input indicating to the
UT69R000 that it has the highest priority. This informs the
UT69R000 to control the Operand buses as soon as the present
bus master relinquishes bus control by asserting BUSY.
Bus Busy (BUSY)
Another bus master generates BUSY input to the UT69R000,
indicating another bus master is using the bus.
Bus Grant Acknowledge (BGACK)
The UT69R000 generates this signal to indicate it is the present
bus master. BGACK enters a high-impedance state when the
UT69R000 gives up control of the Operand buses.
CK4
CK3
CK2
CK1
OSCIN
RISC
ADDRESS
RISC
DATA
ADDRESS VALID (ACC)
NEXT ADDRESS
LRI
DATA VALID (RSn)
NEXT
Figure 19. LRI Instruction Typical Timing
INSTRUCTION
STATE1
OE
WE
相关PDF资料 |
PDF描述 |
|---|---|
| 5962-9855202QZX | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CQFP132 |
| 5962F9855201QZA | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CQFP132 |
| 5962F9855202QYC | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CQFP132 |
| 5962G9855201VZC | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CQFP132 |
| 5962G9855202QYC | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CQFP132 |
相关代理商/技术参数 |
参数描述 |
|---|---|
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