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参数资料
| 型号： | 5962-9855201QZX |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CQFP132 |
| 封装： | QFP-132 |
| 文件页数： | 32/64页 |
| 文件大小： | 1464K |
| 代理商： | 5962-9855201QZX |
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38
Special Source Operand Addressing Modes
In addition to its three direct addressing modes, the UT69R000
also supports three modes of indirect addressing: (1) Data
Register Indirect; (2) Stack Pointer Indirect; and (3) Absolute.
Data Register Indirect
When the UT69R000 uses the Data Register Indirect mode, the
source operand is a memory location addressed by the contents
of the specified data register. The data register is explicitly
stated for all instructions. This mode is only available on the
LR, STR, INR, and STR instructions. The UT69R000 encodes
a 5-bit field, bits 4 through 0, in each instruction as follows:
R0 -- 00000
XR0 -- 10000
R1 -- 00001
R16 -- 10001
R2 -- 00010
XR2 -- 10010
R3 -- 00011
R17 -- 10011
R4 -- 00100
XR4 -- 10100
R5 -- 00101
XR16 -- 10101
R6 -- 00110
XR6 -- 10110
R7 -- 00111
R8 -- 01000
XR8 -- 11000
R9 -- 01001
R18 -- 11001
R10 -- 01010
XR10 -- 11010
R11 -- 01011
R19 -- 11011
R12 -- 01100
XR12 -- 11100
R13 -- 01101
XR18 -- 11101
R14 -- 01110
XR14 -- 11110
R15 -- 01111
Reserved -- 10111
and 11111
Stack Pointer Indirect
When the UT69R000 uses the Stack Pointer Indirect mode, the
source operand is a memory location addressed by the contents
of the Stack Pointer (SP) register. This mode is only available
with POP and PUSH instructions. The UT69R000 encodes a
5-bit field, bits 11 through 15, of each instruction when in the
Stack Pointer Indirect mode as follows:
SP -- 10111.
Absolute
When the UT69R000 uses the Absolute mode, the source
operand is the memory location addressed by the contents of
the 16-bit immediate-data field accompanying the instruction.
This mode is only available on the LR, STR, INR, and OTR
instructions. The system programmer encodes the immediate
data field as a second 16-bit instruction word.
9.4 Data Movement Operations
The UT69R000 places no restrictions on operand size during
data movement. This means the size (Byte, Word, or Long
Word) of the data in the source and destination do not have to
match. The UT69R000 handles the data movement for all
instructions.
When a instruction specifies a word destination, a 16-bit result
is always stored in the destination. If the instruction specifies
a 5-bit literal source operand, then the UT69R000 sign-extends
this source data to produce a 16-bit operand. If the instruction
specifies a word-length source operand, there is no
manipulation of the source data. If the instruction specifies a
long-word source operand, the UT69R000 only retains the least
significant 16 bits of the result. The UT69R000 truncates the
most significant 16 bits of the result.
When a instruction specifies a long-word destination, a 32-bit
result is always stored in the destination. If the instruction
specifies a 5-bit literal source operand, then the UT69R000
sign-extends this source data to produce a 32-bit operand. If
the instruction specifies a word-length source operand, then the
UT69R000 also sign-extends this source data to produce a 32-
bit operand. If the instruction specifies a long-word-length
source operand, there is no manipulation of the source data.
When the system programmer specifies a byte instruction, the
UT69R000 only stores eight bits of the result regardless of
whether the instruction specifies a word or long-word
destination register.
Operation Code Matrix
The UT69R000 performs 30 basic operations, each with its
own operation code. All the UT69R000’s operations are
explicit, and are encoded in bits 14 through 10 of the
instruction.
相关PDF资料 |
PDF描述 |
|---|---|
| 5962-9855202QZX | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CQFP132 |
| 5962F9855201QZA | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CQFP132 |
| 5962F9855202QYC | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CQFP132 |
| 5962G9855201VZC | 32-BIT, 12 MHz, RISC MICROCONTROLLER, CQFP132 |
| 5962G9855202QYC | 32-BIT, 16 MHz, RISC MICROCONTROLLER, CQFP132 |
相关代理商/技术参数 |
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