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| 型号： | 5962R0150201VYC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 32-BIT, 12 MHz, RISC PROCESSOR, CPGA144 |
| 封装： | CERAMIC, PGA-144 |
| 文件页数： | 11/55页 |
| 文件大小： | 685K |
| 代理商： | 5962R0150201VYC |
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19
The RISC Instruction Counter Register (IC) and The RISC
Instruction Register (IR)
The UT1750AR’s RISC interface consists of a 20-bit instruction
address and a 16-bit data bus. The RISC Instruction Counter
Register (IC) supplies the 20-bit address to RISC memory. The
RISC’s instruction data that is read from memory is then input
into the RISC’s Instruction Register (IR). The IR consists of two
sets of latches, a Primary Instruction Register latch (PIR) and
the Instruction Register latch (IRL). These two sets of latches
allow the UT1750AR to perform overlapping memory fetch and
execute cycles. This means the UT1750AR performs a delayed
branch when the flow of the program is interrupted. A delayed
branch implies that the UT1750AR fetches and executes the
instruction following the branch condition BEFORE the
UT1750AR executes the first instruction at the branch location.
The RISC Instruction Register (IR) is made of two 16-bit
latches: the Primary Instruction Register (PIR) latch, and the
Instruction Register (IRL) latch.
The RISC Instruction Counter Save Register (ICS)
The UT1750AR uses the RISC’s Instruction Counter Save
Register (ICS) (figure 20) when servicing interrupts and branch
instructions. When an interrupt or branch occurs, the
UT1750AR saves the IC in the ICS. Read the ICS
IMMEDIATELY after entering the target routine so the return
location can be stored before any other IC saves. The
UT1750AR reads the ICS using the RISC Input instruction. The
configuration of the ICS is shown below.
Pipe Register (PIPE)
The PIPE Register (figure 21) holds the pre-fetched MIL-STD-
1750A instruction. The UT1750AR reads the PIPE Register
with the RISC I/O instruction.
Program Register (PR)
The Program Register holds the present MIL-STD-1750A
instruction. Figure 22 shows the configuration of the Program
Register (PR).
15 14 13 121110 9 8 7
5 4 3 2 1 0
I
C
1
5
I
C
1
4
I
C
1
3
I
C
1
2
I
C
1
I
C
1
0
I
C
9
I
C
8
6
I
C
6
I
C
7
I
C
5
I
C
4
I
C
3
I
C
2
I
C
1
I
C
0
MSB
LSB
Figure 18. RISC Instruction Counter Register (IC)
16
I
C
1
6
17
I
C
1
7
18
I
C
1
8
19
I
C
1
9
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
I
R
1
5
I
R
1
4
I
R
1
3
I
R
1
2
I
R
1
I
R
1
0
I
R
9
I
R
8
6
I
R
6
I
R
7
I
R
5
I
R
4
I
R
3
I
R
2
I
R
1
I
R
0
MSB
LSB
Figure 19. Instruction Register (IR)
2
3
0
15 14 13 121110 9 8 7
5 4 3 2 1 0
I
C
4
5
I
C
5
4
I
C
6
3
I
C
7
2
I
C
8
1
I
C
9
0
I
C
1
I
C
1
6
I
C
1
I
C
1
I
C
1
I
C
1
I
C
1
I
C
1
I
C
1
I
C
1
MSB
LSB
Figure 20. RISC Instruction Counter Save
Register (ICS)
16
I
C
6
17
I
C
7
18
I
C
1
8
19
I
C
9
S S
C
S
C
S
S S S S
S
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
P
I
P
1
5
6
MSB
LSB
Figure 21. The PIPE Register (PIPE)
P
I
P
1
4
P
I
P
1
3
P
I
P
1
2
P
I
P
1
P
I
P
1
0
P
I
P
9
P
I
P
8
P
I
P
7
P
I
P
6
P
I
P
5
P
I
P
4
P
I
P
3
P
I
P
2
P
I
P
1
P
I
P
0
E
E E
E
E E
E E E
E
15 14 13 12 11 10 9
8
7
5
4
3 2
1 0
P
R
1
5
P
R
1
4
P
R
1
3
P
R
1
2
P
R
1
P
R
1
0
P
R
9
P
R
8
6
P
R
6
P
R
7
P
R
5
P
R
4
P
R
3
P
R
2
P
R
1
P
R
0
MSB
LSB
Figure 22. Program Register (PR)
Opcode
IRS
IRD
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