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参数资料
型号： 5962R0722402VYC
厂商： ATMEL CORP
元件分类： 微控制器/微处理器
英文描述： SPECIALTY MICROPROCESSOR CIRCUIT, PQFP256
封装： QFP-256
文件页数： 2/155页
文件大小： 4139K
代理商： 5962R0722402VYC
10
7703D–AERO–12/09
AT697F PRELIMINARY INFORMATION
PR
ELI
MINA
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IN
FOR
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AT
IO
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Pin Description
ATMEL Convention
‘*’ attached to a signal (e.g OE*) designate an active-low signal.
When a bit of a register is writen in C-like style (e.g MCFG2 RAMWWS) it must be read as the
RAMWWS bit in the register MCFG2.
IU and FPU Signals
A[27:0] - Address bus (output)
A[27:0] bus carries the addresses during accesses to external memory. When access to cache
memory is performed, the address of the last external memory access remains driven on the
address bus.
D[31:0] - Data bus (bi-directional)
D[31:0] bus carries the data during accesses to memory. The processor automatically config-
ures the bus as output and drive the lines during write transactions.
During accesses to 8-bit areas, only D[31:24] are used.
CB[7:0] - Check bits (bi-directional)
CB[6:0] bus carries the EDAC checkbits during memory accesses. CB[7]
(1) takes the value of
tcb[7] in the error control register. Processor only drives CB[7:0] during write transactions to
areas programmed to be EDAC protected.
Note:
1. CB[7] is implemented to enable programming of flash memories. When only 7 bits are useful
for EDAC protection, 8 are needed for programming.
Memory Interface
Signals
General management
OE* - Output enable (output)
This active low output is asserted during read transactions on the memory bus.
BRDY* - Bus ready (input)
When driven low, this input indicates to the processor that the current memory access can be
terminated on the next rising clock edge. When driven high, this input indicates to the processor
that it must wait and not end the current access.
READ - Read transaction (output)
This active high output is asserted during read transactions on the memory bus.
WRITE* - Write enable (output)
This active low output provides a write strobe during write transactions on the memory bus.
PROM
ROMS*[1:0] - PROM chip-select (output)
These active low outputs provide the chip-select signal for the PROM area. ROMS*[0] is
asserted when the lower half of the PROM area is accessed (0 - 0x10000000), while ROMS*[1]
is asserted for the upper half.
SRAM
RAMOE*[4:0] - RAM output enable (output)
These active low signals provide an individual output enable for each RAM bank.
RAMS*[4:0] - RAM chip-select (output)
These active low outputs provide the chip-select signals for each RAM bank.
RWE* [3:0] - RAM write enable (output)
These active low outputs provide individual write strobes for each byte. RWEN[0] controls
D[31:24], RWEN[1] controls D[23:16], etc.
I/O
IOS* - I/O select (output)
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