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参数资料
| 型号： | 5962R9653401QXX |
| 元件分类： | 锁存器 |
| 英文描述： | AC SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, CDFP14 |
| 封装： | BOTTOM BRAZED, CERAMIC, DFP-14 |
| 文件页数： | 7/10页 |
| 文件大小： | 233K |
| 代理商： | 5962R9653401QXX |
6
AC ELECTRICAL CHARACTERISTICS 2
(VDD = 5.0V ±10%; VSS = 0V
1, -55
°C < T
C < +125°C); Unless otherwise noted, Tc is per the temperature range ordered.
Notes:
1. Maximum allowable relative shift equals 50mV.
2. All specifications valid for radiation dose
≤ 1E6 rads(Si).
3. Based on characterization, hold time (tH) of 0ns can be assumed if data setup time (tSU2) is >10ns. This is guaranteed, but not tested.
SYMBOL
PARAMETER
MINIMUM
MAXIMUM
UNIT
tPHL
CLK to Q, Q
3
21
ns
tPLH
CLK to Q, Q
1
20
ns
tPLH
PRE to Q
1
15
ns
tPHL
PRE to Q
3
19
ns
tPHL
CLR to Q
3
19
ns
tPLH
CLR to Q
1
15
ns
fMAX
Maximum clock frequency
71
MHz
tSU1
PRE or CLR inactive
Setup time before CLK
↑
5
ns
tSU2
Data setup time before CLK
↑
5
ns
tH
3
Data hold time after CLK
↑
2
ns
tW
Minimum pulse width
PRE or CLR low
CLK high
CLK low
7
ns
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