参数资料
型号: 71M6511H-IGT/F
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64
封装: LEAD FREE, LQFP-64
文件页数: 46/98页
文件大小: 1278K
代理商: 71M6511H-IGT/F
71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
NOVEMBER 2010
Page: 50 of 98
2005–2010 Teridian Semiconductor Corporation
V2.7
A Maxim Integrated Products Brand
Data Flow
The data flow between CE and MPU is shown in Figure 17. In a typical application, the 32-bit compute engine (CE)
sequentially processes the samples from the voltage inputs on pins IA, VA, and IB, performing calculations to measure active
power (Wh), reactive power (VARh), A
2h, and V2h for four-quadrant metering. These measurements are then accessed by the
MPU, processed further and output using the peripheral devices available to the MPU.
CE
MPU
Pre-
Processor
Post-
Processor
IRQ
Processed
Metering
Data
Pulses
I/O RAM (Configuration RAM)
Samples
Data
Figure 17: MPU/CE Data Flow
CE/MPU Communication
Figure 18 shows the functional relationship between CE and MPU. The CE is controlled by the MPU via shared registers in the
I/O RAM and by registers in the CE DRAM. The CE outputs two interrupt signals to the MPU: CE_BUSY and XFER_BUSY,
which are connected to the MPU interrupt service inputs as external interrupts. CE_BUSY indicates that the CE is actively
processing data. This signal will occur once every multiplexer cycle. XFER_BUSY indicates that the CE is updating data to the
output region of the CE RAM. This will occur whenever the CE has finished generating a sum by completing an accumulation
interval determined by SUM_CYCLES * PRE_SAMPS samples. Interrupts to the MPU occur on the falling edges of the
XFER_BUSY and CE_BUSY signals.
Figure 19 shows the sequence of events between CE and MPU upon reset or power-up. In a typical application, the sequence
of events is as follows:
1)
Upon power-up, the MPU initializes the hardware, including disabling the CE
2)
The MPU loads the code for the CE into the CE PRAM
3)
The MPU loads CE data into the CE DRAM.
4)
The MPU starts the CE by setting the CE_EN bit in the I/O RAM.
5)
The CE then repetitively executes its code, generating results and storing them in the CE DRAM
It is important to note that the length of the accumulation interval, as determined by NACC, the product of SUM_CYCLES and
PRE_SAMPS is not an exact multiple of 1000ms. For example, if SUM_CYCLES = 60, and PRE_SAMPS = 00 (42), the resulting
accumulation interval is:
ms
Hz
f
N
S
ACC
75
.
999
62
.
2520
13
32768
42
60
=
=
τ
This means that accurate time measurements should be based on the RTC, not the accumulation interval.
相关PDF资料
PDF描述
71M6511H-IGT 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64
71M6511H-IGTR 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64
71M6521DE-IGTR/F SPECIALTY ANALOG CIRCUIT, QFP64
71M6521DE-IM/F SPECIALTY ANALOG CIRCUIT, QCC68
71M6521FE-IMR/F SPECIALTY ANALOG CIRCUIT, QCC68
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