参数资料
型号: 71M6511H-IGT/F
厂商: MAXIM INTEGRATED PRODUCTS INC
元件分类: 电源管理
英文描述: 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PQFP64
封装: LEAD FREE, LQFP-64
文件页数: 57/98页
文件大小: 1278K
代理商: 71M6511H-IGT/F
71M6511/71M6511H
Single-Phase Energy Meter IC
DATA SHEET
NOVEMBER 2010
Page: 60 of 98
2005–2010 Teridian Semiconductor Corporation
V2.7
A Maxim Integrated Products Brand
DIO_DIR1[7:6]
DIO_DIR1[3:0]
SFR91
R/W
Programs the direction of DIO pins 15, 14 and 11 through 8. 1
indicates output. Ignored if the pin is not configured as I/O.
Note: Bit 4 and Bit 5 must be set to 1.
DIO_DIR2[1:0]
SFRA1[5:0]
R/W
Programs the direction of DIO pins 17 and 16. 1 indicates output.
Ignored if the pin is not configured as I/O.
Note: Bit 2, Bit 3, Bit 4 and Bit 5 must be set to 1.
DIO_0[7:4]
DIO_1[7:6],
DIO_1[3:0]
DIO_2[1:0]
SFR80
SFR90
SFRA0[1:0]
R/W
Port 0
Port 1
Port 2
The value on the DIO pins. Pins configured as LCD will read
zero. When written, changes data on pins configured as
outputs. Pins configured as LCD or input will ignore writes.
DIO_EEX
2008[4]
R/W
When set, converts DIO4 and DIO5 to interface with external
EEPROM. DIO4 becomes SCK and DIO5 becomes bi-directional SDA.
LCD_NUM must be less than 18.
DIO_PV
2008[2]
R/W
Causes VARPULSE to be output on DIO7, if DIO7 is configured as
output. LCD_NUM must be less than 15.
DIO_PW
2008[3]
R/W
Causes WPULSE to be output on DIO6, if DIO6 is configured as
output. LCD_NUM must be less than 17.
EEDATA[7:0]
SFR 9E
R/W
Serial EEPROM interface data
EECTRL[7:0]
SFR 9F
R/W
Serial EEPROM interface control
ECK_DIS
2005[5]
R/W
Emulator clock disable. When one, the emulator clock is disabled.
This bit is to be used with caution! Inadvertently setting
this bit will inhibit access to the part with the ICE
interface and thus preclude flash erase and programming
operations. If ECK_DIS is set, it should be done at least 1000ms after
power-up to give emulators and programming devices enough time to
complete an erase operation.
EQU[2:0]
2000[7:5]
R/W
Specifies the power equation to the CE.
EX_XFR
EX_RTC
2002[0]
2002[1]
R/W
Interrupt enable bits. These bits enable the XFER_BUSY and the
RTC_1SEC interrupts to the MPU. Note that if either interrupt is to be
enabled, EX6 in the 80515 must also be set.
FIR_LEN
2005[4]
R/W
The length of the ADC decimation FIR filter.
1: 22 ADC bits/3 CK32 cycles (384 CKFIR cycles),
0: 21 ADC bits/2 CK32 cycles (288 CKFIR cycles)
FLASH66Z
2005[1]
R/W
Should be set to 1 to minimize supply current.
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