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参数资料
型号： 71M6534H-IGTR/F
厂商： TERIDIAN SEMICONDUCTOR CORP
元件分类： 模拟信号调理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP120
封装： LEAD FREE, LQFP-120
文件页数： 118/124页
文件大小： 2008K
代理商： 71M6534H-IGTR/F
FDS_6533_6534_004
71M6533/71M6534 Data Sheet
v1.1
2007-2009 TERIDIAN Semiconductor Corporation
93
Name
Address
Description
CE
MPU
Type
TEMP FIR data
0x0A
0x28
Input
VBAT FIR data
0x0B
0x2C
Input
…
Internal
…
Chip ID, Version bytes
0x0F
003C
Read
Only
Upper 16 bits are zero. Lower 16 bits are
CHIP_ID[15:8], VERSION[7:0]. This word is
read only.
…
Internal
…
Last Address
0x3FF
0xFFC
Internal
Last Memory Location
4.3.7
CE Status and Control
The CE Status Word is useful for generating early warnings to the MPU (Table 50). It contains sag warn-
ings for phase A, B, and C, as well as F0, the derived clock operating at the fundamental input frequency.
The MPU can read the CE status word at every CE_BUSY interrupt. Since the CE_BUSY interrupt oc-
curs at 2520.6 Hz, it is desirable to minimize the computation required in the interrupt handler of the MPU.
Table 50: CESTATUS Register
CE Address
Name
Description
0x80
CESTATUS
See description of CESTATUS bits in Table 51.
CESTATUS provides information about the status of voltage and input AC signal frequency, which are use-
ful for generating an early power fail warning to initiate necessary data storage. CESTATUS represents
the status flags for the preceding CE code pass (CE_BUSY interrupt). The significance of the bits in
CESTATUS is shown in Table 51.
Table 51: CESTATUS Bit Definitions
CESTATUS
[bit]
Name
Description
31:29
Not Used
These unused bits will always be zero.
28
F0
F0 is a square wave at the exact fundamental input frequency.
27
SAG_C
Normally zero. Becomes one when |VC| remains below SAG_THR for
SAGCNT samples. Will not return to zero until |VC| rises above SAG_THR.
26
SAG_B
Normally zero. Becomes one when VB remains below SAG_THR for
SAG_CNT samples. Will not return to zero until VB rises above SAG_THR.
25
SAG_A
Normally zero. Becomes one when VA remains below SAG_THR for
SAG_CNT samples. Will not return to zero until VA rises above SAG_THR.
24:0
Not Used
These unused bits will always be zero.
The CE is initialized by the MPU using CECONFIG (Table 52). This register contains in packed form
SAG_CNT, FREQSEL0, FREQSEL1, EXT_PULSE, I0_SHUNT, I1_SHUNT, PULSE_SLOW, and PULSE_FAST.
The CECONFIG bit definitions are given in Table 53.
Table 52: CECONFIG Register
CE Ad-
dress
Name
Data
Description
0x20
CECONFIG
0x5020
See description of the CECONFIG bits in Table 53.
The SAG_MASKn bits enable sag detection for the respective phase when set to 1. When SAG_INT is set
to 1, a sag event will generate a transition on the YPULSE output.
相关PDF资料
PDF描述
71M6533-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP100
71M6534-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP120
71M6533-IGTR/F SPECIALTY ANALOG CIRCUIT, PQFP100
71M6534H-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP120
71M6533H-IGT/F SPECIALTY ANALOG CIRCUIT, PQFP100
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