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参数资料
型号： 71M6542F-IGTR/F
厂商： MAXIM INTEGRATED PRODUCTS INC
元件分类： 模拟信号调理
英文描述： SPECIALTY ANALOG CIRCUIT, PQFP100
封装： LEAD FREE, LQFP-100
文件页数： 127/165页
文件大小： 2208K
代理商： 71M6542F-IGTR/F
64
2008–2011 Teridian Semiconductor Corporation
v1.1
Table 53: Data/Direction Registers for SEGDIO16 to SEGDIO31 (71M6542F)
SEGDIO
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Pin #
28
27
25
24
23
22
21
20
19
18
17
16
11
10
9
8
Configuration:
0 = DIO, 1 = LCD
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
LCD_MAP[23:16] (I/O RAM 0x2409)
LCD_MAP[31:24] (I/O RAM 0x2408)
SEG Data Register
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LCD_SEGDIO16[5:0] to LCD_SEGDIO31[5:0]
(I/O RAM 0x2420[5:0] to 0x242F[5:0])
DIO Data Register
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LCD_SEGDIO16[0] to LCD_SEGDIO31[0]
(I/O RAM 0x2420[0] to 0x242F[0])
Direction Register:
0 = input, 1 = output
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
LCD_SEGDIO16[1] to LCD_SEGDIO31[1]
(I/O RAM 0x2420[1] to 0x242F[1])
Table 54: Data/Direction Registers for SEGDIO32 to SEGDIO45 (71M6542F)
SEGDIO
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Pin #
7
6
5
4
3
2
1
100
99
98
97
96
95
94
Configuration:
0 = DIO, 1 = LCD
0
1
2
3
4
5
6
7
0
1
2
3
4
5
LCD_MAP[39:32]
(I/O RAM 0x2407)
LCD_MAP[45:40]
(I/O RAM 0x2406[5:0])
SEG Data Register
32
33
34
35
36
37
38
39
40
41
42
43
44
45
LCD_SEGDIO32[5:0] to LCD_SEGDIO45[5:0]
(I/O RAM 0x2430[5:0] to 0x243D[5:0])
DIO Data Register
32
33
34
35
36
37
38
39
40
41
42
43
44
45
LCD_SEGDIO32[0] to LCD_SEGDIO45[0]
(I/O RAM 0x2430[0] to 0x243D[0])
Direction Register:
0 = input, 1 = output
32
33
34
35
36
37
38
39
40
41
42
43
44
45
LCD_SEGDIO32[1] to LCD_SEGDIO45[1]
(I/O RAM 0x2430[1] to 0x243D[1])
Table 55: Data/Direction Registers for SEGDIO51 to SEGDIO55 (71M6542F)
SEGDIO
51
52
53
54
55
–
Pin #
53
52
51
47
46
–
Configuration:
0 = DIO, 1 = LCD
0
1
2
3
4
–
LCD_MAP[55:51]
(I/O RAM 0x2405[7:3])
SEG Data Register
51
52
53
54
55
–
LCD_SEGDIO51[5:0] to LCD_SEGDIO55[5:0]
(I/O RAM 0x2443[5:0] to 0x2447[5:0])
DIO Data Register
51
52
53
54
55
–
LCD_SEGDIO51[0] to LCD_SEGDIO55[0]
(I/O RAM 0x2443[0] to 0x2447[0])
Direction Register:
0 = input, 1 = output
51
52
53
54
55
–
LCD_SEGDIO51[1] to LCD_SEGDIO55[1]
(I/O RAM 0x2443[1] to 0x2447[1])
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