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参数资料
| 型号： | 72805LB15PFI |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 256 X 18 BI-DIRECTIONAL FIFO, 10 ns, PQFP128 |
| 封装： | TQFP-128 |
| 文件页数： | 16/26页 |
| 文件大小： | 336K |
| 代理商： | 72805LB15PFI |
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72805LB/72815LB/72825LB/72835LB/72845LB CMOS Dual SyncFIFOTM
256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18
OPERATING CONFIGURATIONS
SINGLE DEVICE CONFIGURATION
Each of the two FIFOs contained in a single IDT72805LB/72815LB/
72825LB/72835LB/72845LB may be used as a stand-alone device when
the application requirements are for 256/512/1,024/2,048/4,096 words or
less. These FIFOs are in a single Device Configuration when the First Load
(
FL), Write Expansion In (WXI) and Read Expansion In (RXI) control inputs
are configured as (
FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0), (1,0,1) or
(1,1,0) during reset (Figure 28).
Figure 28. Block Diagram of Single 256 x 18, 512 x 18, 1,024 x 18, 2,048 x 18, 4,096 x 18 Synchronous FIFO
(One of the two FIFOs contained in the IDT72805LB/72815LB/72825LB/72835LB/72845LB)
Figure 29. Block Diagram of the two FIFOs contained in one IDT72805LB/72815LB/72825LB/72835LB/72845LB
configured for a 36-bit Width Expansion
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of FIFO A and B. Status flags can be detected from any one device.
The exceptions are the Empty Flag/Output Ready and Full Flag/Input
Ready. Because of variations in skew between RCLK and WCLK, it is
possible for flag assertion and deassertion to vary by one cycle between
FIFOs. To avoid problems the user must create composite flags by gating
the Empty Flags/Output Ready of every FIFO, and separately gating all Full
Flags/Input Ready. Figure 29 demonstrates a 36-word width by using one
IDT72805LB/72815LB/72825LB/72835LB/72845LBs. Any word width can
be attained by adding additional IDT72805LB/72815LB/72825LB/72835LB/
72845LBs. These FIFOs are in a single Device Configuration when the First
Load (
FL), Write Expansion In (WXI) and Read Expansion In (RXI) control
inputs are configured as (
FL, RXI, WXI = (0,0,0), (0,0,1), (0,1,0), (1,0,0),
(1,0,1) or (1,1,0) during reset (Figure 29). Please see the Application Note
AN-83.
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN)
READ CLOCK (RCLK)
READ ENABLE (
REN)
LOAD (
LD)
OUTPUT ENABLE (
OE)
DATA IN (D0 - D17)
DATA OUT (Q0 - Q17)
FULL FLAG/INPUT READY (
FF/IR)
PROGRAMMABLE (
PAE)
HALF-FULL FLAG (
HF)
EMPTY FLAG/OUTPUT READY (
EF/OR)
PROGRAMMABLE (
PAF)
RESET (
RS)
IDT
72805
72815
72825
72835
72845
3139 drw 28
FL
RXI
WXI
FIFO A OR B
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN)
READ CLOCK (RCLK)
READ ENABLE (
REN)
LOAD (
LD)
OUTPUT ENABLE (
OE)
DATA IN (D)
DATA OUT (Q)
FULL FLAG/INPUT
READY (
FF/IR)
PROGRAMMABLE (
PAE)
HALF FULL FLAG (
HF)
EMPTY FLAG/OUTPUT
READY (
EF/OR)
PROGRAMMABLE (
PAF)
RESET (
RS)
FIFO A
FIFO B
RESET (
RS)
36
18
FF/IR
EF/OR
3139 drw 29
FL
WXI RXI
FL
WXI RXI
FF/IR
EF/OR
NOTE:
1. Do not connect any output control signals directly together.
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相关代理商/技术参数 |
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| 72805LB25BG | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 256 x 18 x 2 121-Pin BGA 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 256 X 18 X 2 121BGA - Rail/Tube |
| 72805LB25BG8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 256 x 18 x 2 121-Pin BGA T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 256 X 18 X 2 121BGA - Tape and Reel |
| 72805LB25PF | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72805LB25PF8 | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
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