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参数资料
| 型号： | 72841L10PF |
| 厂商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分类： | FIFO |
| 英文描述： | 4K X 9 BI-DIRECTIONAL FIFO, 6.5 ns, PQFP64 |
| 封装： | TQFP-64 |
| 文件页数： | 13/16页 |
| 文件大小： | 211K |
| 代理商： | 72841L10PF |
6
IDT72801/728211/72821/72831/72841/72851 DUAL CMOS SyncFIFOTM
DUAL 256 x 9, DUAL 512 x 9, DUAL 1K x 9, DUAL 2K x 9, DUAL 4K x 9, DUAL 8K x 9
COMMERCIAL AND INDUSTRIAL
TEMPERATURERANGES
When either of the two Read Enable
RENA1, RENA2 (RENB1, RENB2)
associated with FIFO A (B) is HIGH, the output register holds the previous data
and no new data is allowed to be loaded into the register.
WhenallthedatahasbeenreadfromFIFOA(B),theEmptyFlag
EFA(EFB)
willgoLOW,inhibitingfurtherreadoperations. Onceavalidwriteoperationhas
been accomplished,
EFA(EFB) will go HIGH after tREF and a valid read can
begin. The Read Enables
RENA1, RENA2(RENB1, RENB2)areignoredwhen
FIFO A (B) is empty.
OutputEnable(
OEA,OEB)—WhenOutputEnableOEA(OEB)isenabled
(LOW),theparalleloutputbuffersofFIFOA(B)receivedatafromtheirrespective
output register. When Output Enable
OEA(OEB) is disabled (HIGH), the QA
(QB) output data bus is in a high-impedance state.
Write Enable 2/Load (WENA2/
LDA, WENB2/LDB) — This is a dual-
purpose pin. FIFO A (B) is configured at Reset to have programmable flags
or to have two write enables, which allows depth expansion. If WENA2/
LDA
(WENB2/
LDB) issetHIGHatResetRSA=LOW(RSB = LOW),thispinoperates
as a second write enable pin.
If FIFO A (B) is configured to have two write enables, when Write Enable
1
WENA1(WENB1)isLOWandWENA2/LDA(WENB2/LDB)isHIGH,datacanbe
loaded into the input register and RAM array on the LOW-to-HIGH transition
of every Write Clock WCLKA (WCLKB). Data is stored in the array sequentially
and independently of any ongoing read operation.
In this configuration, when
WENA1(WENB1)isHIGHand/orWENA2/LDA
(WENB2/
LDB)isLOW,theinputregisterofArrayAholdsthepreviousdataand
no new data is allowed to be loaded into the register.
To prevent data overflow, the Full Flag
FFA (FFB) will go LOW, inhibiting
further write operations. Upon the completion of a valid read cycle,
FFA(FFB)
will go HIGH after tWFF, allowing a valid write to begin.
WENA1, (WENB1)and
WENA2/
LDA (WENB2/LDB) are ignored when the FIFO is full.
FIFO A (B) is configured to have programmable flags when the WENA2/
LDA(WENB2/LDB)issetLOWatResetRSA = LOW(RSB=LOW). EachFIFO
contains four 8-bit offset registers which can be loaded with data on the inputs,
or read on the outputs. See Figure 3 for details of the size of the registers and
the default values.
If FIFO A (B) is configured to have programmable flags, when the
WENA1
(
WENB1) and WENA2/LDA (WENB2/LDB) are set LOW, data on the DA (DB)
inputs are written into the Empty (Least Significant Bit) Offset register on the first
LOW-to-HIGH transition of the WCLKA (WCLKB). Data are written into the
Empty (Most Significant Bit) Offset register on the second LOW-to-HIGH
transitionofWCLKA(WCLKB),intotheFull(LeastSignificantBit)Offsetregister
on the third transition, and into the Full (Most Significant Bit) Offset register on
the fourth transition. The fifth transition of WCLKA (WCLKB) again writes to the
Empty (Least Significant Bit) Offset register.
However, writing all offset registers does not have to occur at one time. One
ortwooffsetregisterscanbewrittenandthenbybringing
LDA(LDB)HIGH,FIFO
A (B) is returned to normal read/write operation. When
LDA (LDB) is set LOW,
and
WENA1(WENB1)isLOW,thenextoffsetregisterinsequenceiswritten.
ThecontentsoftheoffsetregisterscanbereadontheQA(QB)outputs when
WENA2/
LDA(WENB2/LDB)issetLOWandbothReadEnablesRENA1,RENA2
(
RENB1,RENB2)aresetLOW. DatacanbereadontheLOW-to-HIGHtransition
of the Read Clock RCLKA (RCLKB).
SIGNAL DESCRIPTIONS
FIFO A and FIFO B are identical in every respect. The following description
explainstheinteractionofinputandoutputsignalsforFIFOA.Thecorrespond-
ing signal names for FIFO B are provided in parentheses.
INPUTS:
Data In (DA0 – DA8, DB0 – DB8)
— DA0 - DA8 are the nine data inputs
for memory array A. DB0 - DB8 are the nine data inputs for memory array B.
CONTROLS:
Reset
(RSA, RSB)—ResetofFIFOA(B)isaccomplishedwheneverRSA
(
RSB) input is taken to a LOW state. During Reset, the internal read and write
pointersassociatedwiththeFIFOaresettothefirstlocation.AResetisrequired
afterpower-upbeforeawriteoperationcantakeplace. TheFullFlag
FFA(FFB)
and Programmable Almost-Full flag
PAFA(PAFB) will be reset to HIGH after
tRSF. TheEmptyFlag
EFA(EFB)andProgrammableAlmost-EmptyflagPAEA
(
PAEB) will be reset to LOW after tRSF. During Reset, the output register is
initializedtoallzerosandtheoffsetregistersareinitializedtotheirdefaultvalues.
Write Clock (WCLKA, WCLKB) — A write cycle to Array A (B) is
initiated on the LOW-to-HIGH transition of WCLKA (WCLKB). Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of
WCLKA (WCLKB). The Full Flag
FFA(FFB) and Programmable Almost-Full
flag
PAFA(PAFB)aresynchronizedwithrespecttotheLOW-to-HIGHtransition
of the Write Clock WCLKA (WCLKB).
The Write and Read Clocks can be asynchronous or coincident.
Write Enable 1 (
WENA1, WENB1) — If FIFO A (B) is configured for
programmable flags,
WENA1 (WENB1) is the only enable control pin. In this
configuration, when
WENA1(WENB1)isLOW,datacanbeloadedintotheinput
register of RAM Array A (B) on the LOW-to-HIGH transition of every Write Clock
WCLKA (WCLKB). Data is stored in Array A (B) sequentially and independently
of any ongoing read operation.
Inthisconfiguration,when
WENA1(WENB1)isHIGH,theinputregisterholds
the previous data and no new data is allowed to be loaded into the register.
If the FIFO is configured to have two write enables, which allows for depth
expansion. See Write Enable 2 paragraph below for operation in this
configuration.
To prevent data overflow,
FFA (FFB) will go LOW, inhibiting further write
operations. Upon the completion of a valid read cycle, the
FFA(FFB)willgoHIGH
after tWFF, allowing a valid write to begin.
WENA1(WENB1)isignoredwhenFIFO
A (B) is full.
Read Clock (RCLKA, RCLKB) — Data can be read from Array A (B) on
the LOW-to-HIGH transition of RCLKA (RCLKB). The Empty Flag
EFA(EFB)
and Programmable Almost-Empty Flag
PAEA(PAEB) are synchronized with
respect to the LOW-to-HIGH transition of RCLKA (RCLKB).
The Write and Read Clocks can be asynchronous or coincident.
Read Enables (
RENA1, RENA2, RENB1, RENB2) — When both Read
Enables
RENA1, RENA2 (RENB1, RENB2) are LOW, data is read from Array
A (B) to the output register on the LOW-to-HIGH transition of the Read Clock
RCLKA (RCLKB).
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相关代理商/技术参数 |
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| 72841L10PF8 | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72841L10PFG | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72841L10PFG8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin TQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 4KX9X2 64TQFP - Tape and Reel |
| 72841L10TF | 功能描述:先进先出 RoHS:否 制造商:IDT 电路数量: 数据总线宽度:18 bit 总线定向:Unidirectional 存储容量:4 Mbit 定时类型:Synchronous 组织:256 K x 18 最大时钟频率:100 MHz 访问时间:10 ns 电源电压-最大:3.6 V 电源电压-最小:6 V 最大工作电流:35 mA 最大工作温度:+ 85 C 封装 / 箱体:TQFP-80 封装: |
| 72841L10TF8 | 制造商:Integrated Device Technology Inc 功能描述:FIFO Mem Sync Quad Depth/Width Bi-Dir 4K x 9 x 2 64-Pin STQFP T/R 制造商:Integrated Device Technology Inc 功能描述:FIFO SYNC QUAD DEPTH/WIDTH BI-DIR 4KX9X2 64TQFP - Tape and Reel |
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