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| 型号： | 73M1916-IMR/F |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 42/88页 |
| 文件大小： | 0K |
| 描述： | MICRODAA SET FXO OF VOIP 32-QFN |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 2,500 |
| 系列： | MicroDAA™ |
| 功能： | 数据存取装置（DAA） |
| 接口： | PCM，SPI |
| 电路数： | 1 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 32-VFQFN 裸露焊盘 |
| 供应商设备封装： | 32-QFN 裸露焊盘（5x5） |
| 包装： | 带卷 (TR) |
| 包括： | * |
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DS_1x66B_001
73M1866B/73M1966B Data Sheet
Rev. 1.6
47
8.2
PCM Clock Frequencies
The 73M1x66B supports the following PCLK input frequencies:
256 kHz
512 kHz
768 kHz
1.024 MHz
1.536 MHz
1.544 MHz
2.048 MHz
3.088 MHz
4.096 MHz
6.176 MHz
8.192 MHz
The 73M1x66B automatically detects the frequency of PCLK and adjusts its internal PLL parameters
accordingly. At startup, the first eight frames are discarded. The next eight frames are used to count the
number of PCLK cycles during each frame. If the count differs among these eight frames or if the count is
a non-supported value, then a PCLKDT interrupt is asserted.
If PCLK is set at a frequency different from the above list, the PLL will be set for a PCLK of 2.048 MHz.
Since there will be a discrepancy between the frequency of PCLK and the frequency considered for PLL
settings, a PCLKDT interrupt may occur if required. It takes about 20 PCM frames before PLL is locked,
which is shown through the assertion of the FRCVCO status bit. PCLK must be running for several
cycles when reset is de-asserted. After that point, SPI transactions can start.
8.3
Master Mode
The default mode of operation for the PCM highway in the 73M1x66B is the slave mode i.e.,
FS and
PCLK are inputs to the device. The 73M1x66B offers a master mode by which a 4.096 MHz clock is
applied to the PCLKI pin. The master clock is divided by two to generate a 2.048 MHz clock that is
connected to the PCM highway via the PCLKO pin. Similarly,
FS of one 2.048 MHz period long is
generated and driven to the PCM highway.
The master mode is set by setting the MASTER bit.
8.4
A-
law / μ-law Compander
The 73M1x66B may be programmed for compressed A-
law mode, compressed μ-law mode, or linear
mode. Compression schemes are used to minimize the bandwidth required for exchanging data samples
on the PCM highway. For instance, when PCLK is 8.192 MHz there are 128 8-bit time slots available.
The density of the overall system is halved when working in linear mode, which requires 16-bit time slots.
The 73M1x66B fully complies with the A-
law and μ-law companding specifications defined in the ITU-T
Recommendation G.711.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| 73M1916-IVT/F | 功能描述:电信线路管理 IC DAA-FXO VOLP System Line Side RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| 73M1916-IVTR/F | 功能描述:电信线路管理 IC DAA-FXO VOLP System Line Side RoHS:否 制造商:STMicroelectronics 产品:PHY 接口类型:UART 电源电压-最大:18 V 电源电压-最小:8 V 电源电流:30 mA 最大工作温度:+ 85 C 最小工作温度:- 40 C 安装风格:SMD/SMT 封装 / 箱体:VFQFPN-48 封装:Tray |
| 73M1922-DB | 功能描述:网络开发工具 73M1922 Demo Brd RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| 73M1966B-DB | 功能描述:网络开发工具 73M1966B Demo Brd RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
| 73M1966B-DB-C | 功能描述:网络开发工具 73M1966B Demo Brd w/GUI Cable RoHS:否 制造商:Rabbit Semiconductor 产品:Development Kits 类型:Ethernet to Wi-Fi Bridges 工具用于评估:RCM6600W 数据速率:20 Mbps, 40 Mbps 接口类型:802.11 b/g, Ethernet 工作电源电压:3.3 V |
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