参数资料
型号: 73S1209F-44IMR/F/P
厂商: Maxim Integrated Products
文件页数: 65/123页
文件大小: 0K
描述: IC SMART CARD READER PROG 44-QFN
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 2,500
系列: 73S12xx
核心处理器: 80515
芯体尺寸: 8-位
速度: 24MHz
连通性: I²C,智能卡,UART/USART
外围设备: LED,POR,WDT
输入/输出数: 9
程序存储器容量: 32KB(32K x 8)
程序存储器类型: 闪存
RAM 容量: 2K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 44-VFQFN 裸露焊盘
包装: 带卷 (TR)
73S1209F Data Sheet
DS_1209F_004
Timer/Counter Control Register (TCON): 0x88
0x00
Table 43: The TCON Register
MSB
LSB
TF1
TR1
TF0
TR0
IE1
IT1
IE0
IT0
Bit
Symbol
Function
TCON.7
TF1
The Timer 1 overflow flag is set by hardware when Timer 1 overflows.
This flag can be cleared by software and is automatically cleared when
an interrupt is processed.
TCON.6
TR1
Timer 1 Run control bit. If cleared, Timer 1 stops.
TCON.5
TF0
Timer 0 overflow flag set by hardware when Timer 0 overflows. This
flag can be cleared by software and is automatically cleared when an
interrupt is processed.
TCON.4
TR0
Timer 0 Run control bit. If cleared, Timer 0 stops.
TCON.3
IE1
External Interrupt 1 edge flag.
TCON.2
IT1
External interrupt 1 type control bit.
TCON.1
IE0
External Interrupt 0 edge flag.
TCON.0
IT0
External Interrupt 0 type control bit.
1.7.6 WD Timer (Software Watchdog Timer)
The software watchdog timer is a 16-bit counter that is incremented once every 24 or 384 clock cycles.
After a reset, the watchdog timer is disabled and all registers are set to zero. The watchdog consists of a
16-bit counter (WDT), a reload register (WDTREL), prescalers (by 2 and by 16), and control logic. Once
the watchdog starts, it cannot be stopped unless the internal reset signal becomes active.
WD Timer Start Procedure: The WDT is started by setting the SWDT flag. When the WDT register
enters the state 0x7CFF, an asynchronous WDTS signal will become active. The signal WDTS sets bit 6
in the IP0 register and requests a reset state. WDTS is cleared either by the reset signal or by changing
the state of the WDT timer.
Refreshing the WD Timer: The watchdog timer must be refreshed regularly to prevent the reset request
signal from becoming active. This requirement imposes an obligation on the programmer to issue two
instructions. The first instruction sets WDT and the second instruction sets SWDT. The maximum delay
allowed between setting WDT and SWDT is 12 clock cycles. If this period has expired and SWDT has
not been set, WDT is automatically reset, otherwise the watchdog timer is reloaded with the content of
the WDTREL register and WDT is automatically reset.
46
Rev. 1.2
相关PDF资料
PDF描述
73S1209F-44IM/F/P IC SMART CARD READER PROG 44-QFN
AKSPT-G-BLU-R CONN SHUNT 2.54MM GOLD 6.0MM BLU
AKSNT-Z-RED-R CONN SHUNT 2.54MM TIN 4.5MM RED
AKSNT-Z-BLUE-R CONN SHUNT 2.54MM TIN 4.5MM BLUE
EDJ4G0 SHUNT .100" BLACK W/HANDLE
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