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| 型号： | 73S1215F-EB-LITE |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 113/136页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL 73S1215F CBL/DOC/CD |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 系列： | * |
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73S1215F Data Sheet
DS_1215F_003
78
Rev. 1.4
1.7.15.1 ISO 7816 UART
An embedded ISO 7816 (hardware) UART is provided to control communications between a smart card
and the 73S1215F MPU. The UART can be shared between the one built-in ICC interface and the
external ICC interface. Selection of the desired interface is made by register SCSel. Control of the
external interface is handled by the I
2C interface for any external 8010 devices. The following is a list of
features for the ISO 7816 UART:
Two-byte FIFO for temporary data storage on both TX and Rx data.
Parity checking in T=0. This feature can be enabled/disabled by firmware. Parity error reporting to
firmware and Break generation to ICC can be controlled independently.
Parity error generation for test purposes.
Retransmission of last byte if ICC indicates T=0 parity error. This feature can be enabled/disabled by
firmware.
Deletion of last byte received if ICC indicates T=0 parity error. This feature can be enabled/disabled
by firmware.
CRC/LRC generation and checking. CRC/LRC is automatically inserted into T=1 data stream by the
hardware. This feature can be enabled/disabled by firmware.
Support baud rates: 230000, 115200, 57600, 38400, 28800, 19200, 14400, 9600 under firmware
control (assuming 12MHz crystal) with various F/D settings
Firmware manages F/D. All F/D combinations are supported in which F/D is directly divisible by 31 or
32 (i.e. F/D is a multiple of either 31 or 32).
Flexible ETU clock generation and control.
Detection of convention (direct or indirect) character TS. This affects both polarity and order of bits in
byte. Convention can be overridden by firmware.
Supports WTX Timeout with an expanded Wait Time Counter (28 bits).
A Bypass Mode is provided to bypass the hardware UART in order for the software to emulate the
UART (for non-standard operating modes). In such a case, the I/O line value is reflected in SFR
some synchronous and non T=0 / T=1 cards.
The single integrated smart card UART is capable of supporting T=0 and T=1 cards in hardware
therefore offloading the bit manipulation tasks from the firmware. The embedded firmware instructs the
hardware which smart card it should communicate with at any point in time. Firmware reconfigures the
UART as required when switching between smart cards. When the 73S1215F has transmitted a
message with an expected response, the firmware should not switch the UART to another smart card
until the first smart card has responded. If the smart card responds while another smart card is selected,
that first smart card’s response will be ignored.
1.7.15.2 Answer to Reset Processing
A card insertion event generates an interrupt to the firmware, which is then responsible for the
configuration of the electrical interface, the UART and activation of the card. The activation sequencer
goes through the power up sequence as defined in the ISO 7816-3 specification. An asynchronous
activation timing diagram is shown in Figure 17. After the card RST is de-asserted, the firmware instructs
the hardware to look for a TS byte that begins the ATR response. If a response is not provided within the
pre-programmed timeout period, an interrupt is generated and the firmware can then take appropriate
action, including instructing the 73S1215F to begin a deactivation sequence. Once commanded, the
deactivation sequencer goes through the power down sequence as defined in the ISO 7816-3
specification. If an ATR response is received, the hardware looks for a TS byte that determines
direct/inverse convention. The hardware handles the indirect convention conversion such that the
embedded firmware only receives direct convention. This feature can be disabled by firmware within
SByteCtl register. Parity checking and break generation is performed on the TS byte unless disabled by
firmware. If during the card session, a card removal, over-current or other error event is detected, the
hardware will automatically perform the deactivation sequence and then generate an interrupt to the
firmware. The firmware can then perform any other error handling required for proper system operation.
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| 73S1217F | 制造商:TERIDIAN 制造商全称:TERIDIAN 功能描述:Bus-Powered 80515 System-on-Chip with USB, ISO 7816 / EMV, PINpad and More |
| 73S1217F-68IM/F | 功能描述:8位微控制器 -MCU Bus Pwr’d 80515 SoC w/USB 7816/EMV PINpd RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
| 73S1217F-68IM/F/P | 功能描述:IC SMART CARD READER PROG 68-QFN RoHS:是 类别:集成电路 (IC) >> 嵌入式 - 微控制器， 系列:73S12xx 产品培训模块:MCU Product Line Introduction AVR® UC3 Introduction 标准包装:2,500 系列:AVR®32 UC3 B 核心处理器:AVR 芯体尺寸:32-位 速度:60MHz 连通性:I²C，IrDA，SPI，SSC，UART/USART，USB 外围设备:欠压检测/复位，DMA，POR，PWM，WDT 输入/输出数:28 程序存储器容量:128KB（128K x 8） 程序存储器类型:闪存 EEPROM 大小:- RAM 容量:32K x 8 电压 - 电源 (Vcc/Vdd):1.65 V ~ 1.95 V 数据转换器:A/D 6x10b 振荡器型:内部 工作温度:-40°C ~ 85°C 封装/外壳:48-TQFP 包装:带卷 (TR) 配用:ATSTK600-TQFP48-ND - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT-ND - KIT AVR/AVR32 DEBUGGER/PROGRMMRATEVK1101-ND - KIT DEV/EVAL FOR AVR32 AT32UC3B 其它名称:AT32UC3B1128-AUR-NDAT32UC3B1128-AURTR |
| 73S1217F-68IMR/F | 功能描述:8位微控制器 -MCU Bus Pwr’d 80515 SoC w/USB 7816/EMV PINpd RoHS:否 制造商:Silicon Labs 核心:8051 处理器系列:C8051F39x 数据总线宽度:8 bit 最大时钟频率:50 MHz 程序存储器大小:16 KB 数据 RAM 大小:1 KB 片上 ADC:Yes 工作电源电压:1.8 V to 3.6 V 工作温度范围:- 40 C to + 105 C 封装 / 箱体:QFN-20 安装风格:SMD/SMT |
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