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参数资料
| 型号： | 73S8023C-IMR/F |
| 厂商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | SPECIALTY ANALOG CIRCUIT, QCC32 |
| 封装： | 5 X 5 MM, LEAD FREE, QFN-32 |
| 文件页数： | 6/27页 |
| 文件大小： | 389K |
| 代理商： | 73S8023C-IMR/F |
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73S8023C Data Sheet
DS_8023C_019
14
Rev. 1.5
8.4
Deactivation Sequence (Asynchronous Mode)
Deactivation is initiated either by the system controller by setting
CMDVCC high, or automatically in the
event of hardware faults. Hardware faults are over-current, overheating, VDD fault, VCC
1.
RST goes low at the end of time t
fault, and card
extraction during the session.
The following steps list the deactivation sequence and the timing of the card control signals when the
system controller sets the
CMDVCC high or OFF goes low due to a fault or card removal:
1
2.
CLK stops low at the end of time t
.
2
3.
I/O goes low at the end of time t
.
3
4.
V
. Out of reception mode.
CC is shut down at the end of time t 4. After a delay t 5 (discharge of the V CC capacitor), VCC is low.
RST
CLK
I/O
VCC
t
1
t
2
t
3
t
4
t
5
CMDVCC
-- OR --
OFF
Figure 7: Asynchronous Deactivation Sequence
9
OFF and Fault Detection
There are two cases for which the system controller can monitor the
OFF signal: to query regarding the
card presence outside card sessions, or for fault detection during card sessions.
Monitoring Outside a Card Session
In this condition,
CMDVCC is always high, OFF is low if the card is not present, and high if the card is
present. Because it is outside a card session, any fault detection will not act upon the
OFF signal. No
deactivation is required during this time.
Monitoring During a Card Session
CMDVCC is always low, and OFF falls low if the card is extracted or if any fault is detected. At the same
time that
OFF is set low, the sequencer starts the deactivation process.
Figure 8 shows the timing diagram for the signals
CMDVCC, PRES, and OFF during a card session and
outside the card session:
t1
≥ 0.5 s, timing by 1.5 MHz internal Oscillator
t2
≥ 7.5 s
t3
≥ 0.5 s
t4
≥ 0.5 s
t5 = depends on VCC filter capacitor.
t1 + t2 + t3 + t4 + t5 ~= 100 s
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