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参数资料
型号： 74AHC377
厂商： NXP Semiconductors N.V.
英文描述： Octal D-type flip-flop with data enable; positive-edge trigger
中文描述： 八路D型触发器数据使触发器，积极边缘触发
文件页数： 2/20页
文件大小： 101K
代理商： 74AHC377
2000 Aug 15
2
Philips Semiconductors
Product specification
Octal D-type flip-flop with data enable;
positive-edge trigger
74AHC377; 74AHCT377
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
CDM EIA/JESD22-C101 exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger actions
Inputs accept voltages higher than V
CC
Ideal for addressable register applications
Data enable for address and data synchronization
Eight positive-edge triggered D-type flip-flops
See “273” for master reset version
See “373” for transparent latch version
See “374” for 3-state version
For AHC only: operates with CMOS input levels
For AHCT only: operates with TTL input levels
Specified from
40 to +85 and from
40 to +125
°
C.
DESCRIPTION
The 74AHC/AHCT377 D-type flip-flops are high-speed
silicon-gate CMOS devices and are pin compatible with
low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT377 devices have eight edge-triggered,
D-type flip-flops with individual D inputs and Q outputs.
A common clock (CP) input loads all flip-flops
simultaneously when the data enable (E) is LOW. The
state of each D input, one set-up time before the
LOW-to-HIGH clock transition, is transferred to the
corresponding output (Q
n
) of the flip-flop.
TheE input must be stable only one set-up time prior to the
LOW-to-HIGH transition for predictable operation.
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
AHC
AHCT
t
PHL
/t
PLH
propagation delay;
CP to Q
n
maximum clock frequency
input capacitance
power dissipation
capacitance
C
L
= 15 pF; V
CC
= 5 V
3.9
4.0
ns
f
max
C
I
C
PD
C
L
= 15 pF; V
CC
= 5 V
V
I
= V
CC
or GND
C
L
= 50 pF; f = 1 MHz;
notes 1 and 2
175
3.0
20
140
3.0
23
MHz
pF
pF
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