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参数资料
| 型号： | 74AHCU04 |
| 厂商： | NXP Semiconductors N.V. |
| 元件分类： | 电容 |
| 英文描述： | CERAMIC CHIP/MIL-PRF-55681 |
| 中文描述： | 陶瓷芯片/mil-prf-55681 |
| 文件页数： | 2/16页 |
| 文件大小： | 87K |
| 代理商： | 74AHCU04 |
1999 Sep 27
2
Philips Semiconductors
Product specification
Hex inverter
74AHCU04
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Inputsacceptsvoltageshigherthan
V
CC
Specified from
40 to +85 and +125
°
C.
DESCRIPTION
The74AHCU04ishigh-speedSi-gate
CMOS devices and is pin compatible
with low power Schottky TTL
(LSTTL). It is specified in compliance
with JEDEC standard No. 7A.
The 74AHCU04 is a general purpose
hex inverter. Each of the six inverters
is a single stage.
FUNCTION TABLE
See note 1.
Note
1.
H = HIGH voltage level;
L = LOW voltage level.
INPUT nA
OUTPUT nY
L
H
H
L
QUICK REFERENCE DATA
GND = 0 V; T
amb
= 25
°
C; t
r
= t
f
≤
3.0 ns.
Notes
1.
C
PD
is used to determine the dynamic power dissipation (P
D
in
μ
W).
P
D
= C
PD
×
V
CC2
×
f
i
+
∑
(C
L
×
V
CC2
×
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
∑
(C
L
×
V
CC2
×
f
o
) = sum of outputs;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in Volts.
The condition is V
I
= GND to V
CC
.
2.
PINNING
SYMBOL
PARAMETER
CONDITIONS
TYPICAL
UNIT
t
PHL
/t
PLH
propagation delay
nA to nY
input capacitance
output capacitance
power dissipation
capacitance
C
L
= 15 pF;
V
CC
= 5 V
V
I
= V
CC
or GND
1.5
ns
C
I
C
O
C
PD
3.0
4.0
9.1
pF
pF
pF
C
L
= 50 pF;
f = 1 MHz;
notes 1 and 2
PIN
SYMBOL
DESCRIPTION
1, 3, 5, 9, 11 and 13
2, 4, 6, 8, 10 and 12
7
14
1A to 6A
1Y to 6Y
GND
V
CC
data inputs
data outputs
ground (0 V)
DC supply voltage
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